diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-22 11:42:32 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-22 11:42:32 +0000 |
commit | c02b4fc9db3c3c1e263027382697b566127f66bb (patch) | |
tree | 11bd18488e360e5c1beeb9ccb852ef4489c3689a /src/southbridge/intel/i82801bx/i82801bx_ide.c | |
parent | 27852aba6787617ca5656995cbc7e8ef0a3ea22c (diff) | |
download | coreboot-c02b4fc9db3c3c1e263027382697b566127f66bb.tar.xz |
printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801bx/i82801bx_ide.c')
-rw-r--r-- | src/southbridge/intel/i82801bx/i82801bx_ide.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c index 9bfab00399..ffbaf80dbd 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_ide.c +++ b/src/southbridge/intel/i82801bx/i82801bx_ide.c @@ -43,9 +43,9 @@ static void ide_init(struct device *dev) if (!config || config->ide0_enable) { /* Enable primary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE0: Primary IDE interface is enabled\n"); + printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n"); } else { - printk_info("IDE0: Primary IDE interface is disabled\n"); + printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -54,9 +54,9 @@ static void ide_init(struct device *dev) if (!config || config->ide1_enable) { /* Enable secondary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE1: Secondary IDE interface is enabled\n"); + printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n"); } else { - printk_info("IDE1: Secondary IDE interface is disabled\n"); + printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); } |