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authorStefan Reinauer <stepan@coresystems.de>2010-03-28 15:11:56 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-28 15:11:56 +0000
commit83a1dd850b9f61929a2db17a9429d3d193e34bfb (patch)
treec3f0ab1329b7a882fccf8553842961f57b556c1b /src/southbridge/intel/i82801bx
parentf733d4754438f7289dd84d19871c7fe0a322801e (diff)
downloadcoreboot-83a1dd850b9f61929a2db17a9429d3d193e34bfb.tar.xz
drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be looking for.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801bx')
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h
index 6d77f81985..8c2c30794c 100644
--- a/src/southbridge/intel/i82801bx/i82801bx.h
+++ b/src/southbridge/intel/i82801bx/i82801bx.h
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
#define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
-#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801bx_enable(device_t dev);
#endif