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| author | Steven J. Magnani <steve@digidescorp.com> | 2005-09-14 15:34:03 +0000 |
|---|---|---|
| committer | Steven J. Magnani <steve@digidescorp.com> | 2005-09-14 15:34:03 +0000 |
| commit | 706aed8eb9c1836d1b6c53b081f789a1d3afaa25 (patch) | |
| tree | 953355608f5491e7e046a30e0cba007e27522bf9 /src/southbridge/intel/i82801ca/i82801ca_pci.c | |
| parent | 09e4ef670245566f1ee50759976babac17aae55d (diff) | |
| download | coreboot-706aed8eb9c1836d1b6c53b081f789a1d3afaa25.tar.xz | |
Initial revision.
Based on i82801er and LB v1 code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801ca/i82801ca_pci.c')
| -rw-r--r-- | src/southbridge/intel/i82801ca/i82801ca_pci.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801ca/i82801ca_pci.c b/src/southbridge/intel/i82801ca/i82801ca_pci.c new file mode 100644 index 0000000000..d5355cb62a --- /dev/null +++ b/src/southbridge/intel/i82801ca/i82801ca_pci.c @@ -0,0 +1,30 @@ +#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "i82801ca.h"
+
+static void pci_init(struct device *dev)
+{
+ // NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F)
+ /* Enable pci error detecting */
+ uint32_t dword = pci_read_config32(dev, PCI_COMMAND);
+ dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
+ pci_write_config32(dev, PCI_COMMAND, dword);
+}
+
+static struct device_operations pci_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pci_init,
+ .scan_bus = pci_scan_bridge,
+};
+
+static struct pci_driver pci_driver __pci_driver = {
+ .ops = &pci_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82801CA_PCI,
+};
+
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