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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-11-04 03:21:37 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-11-04 03:21:37 +0000 |
| commit | a29ec0633ad1cd277c17bba87d5094b2f981e726 (patch) | |
| tree | daf386bf9b8e7f9d44aeff74d67137a1170dfd46 /src/southbridge/intel/i82801dbm/i82801dbm.c | |
| parent | 02b2365f02cd987b7d4306a82bccaad19494443d (diff) | |
| download | coreboot-a29ec0633ad1cd277c17bba87d5094b2f981e726.tar.xz | |
Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up to
ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements.
Use human-readable names for the PCI ID #defines.
Rename *_ISA to *_LPC as per datasheet.
The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error.
The fixes in southbridge code are only to keep the build working for now,
any real improvements will only go into the 82801xx code in future.
This is abuild-tested so it shouldn't break anything.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801dbm/i82801dbm.c')
0 files changed, 0 insertions, 0 deletions