sb/intel/i82801dx: Drop GNVS in SMM

The table in CBMEM was never allocated with i82801dx.

Change-Id: I4ad97f6504e0f1b22d16210b7dbf5164852cb232
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42851
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 83 deletions

diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 7cd5c7056c..b54d1d39c5 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -19,8 +19,6 @@
 #define   G_SMRANE	(1 << 3)
 #define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
-#include "nvs.h"
-
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
  */
@@ -30,13 +28,6 @@ unsigned char *mbi = NULL;
 u32 mbi_len;
 u8 mbi_initialized = 0;
 
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
- * by coreboot.
- */
-struct global_nvs *gnvs = (struct global_nvs *)0x0;
-void *tcg = (void *)0x0;
-void *smi1 = (void *)0x0;
-
 /**
  * @brief read and clear PM1_STS
  * @return PM1_STS register
@@ -188,23 +179,6 @@ static void dump_tco_status(u32 tco_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-int southbridge_io_trap_handler(int smif)
-{
-	switch (smif) {
-	case 0x32:
-		printk(BIOS_DEBUG, "OS Init\n");
-		/* gnvs->smif:
-		 *  On success, the IO Trap Handler returns 0
-		 *  On failure, the IO Trap Handler returns a value != 0
-		 */
-		gnvs->smif = 0;
-		return 1; /* IO trap handled */
-	}
-
-	/* Not handled */
-	return 0;
-}
-
 /**
  * @brief Set the EOS bit
  */
@@ -482,62 +456,6 @@ static void southbridge_smi_periodic(void)
 	printk(BIOS_DEBUG, "Periodic SMI.\n");
 }
 
-static void southbridge_smi_monitor(void)
-{
-#define IOTRAP(x) (trap_sts & (1 << x))
-#if 0
-	u32 trap_sts, trap_cycle;
-	u32 data, mask = 0;
-	int i;
-
-	trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
-	RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
-
-	trap_cycle = RCBA32(0x1e10);
-	for (i=16; i<20; i++) {
-		if (trap_cycle & (1 << i))
-			mask |= (0xff << ((i - 16) << 2));
-	}
-
-
-	/* IOTRAP(3) SMI function call */
-	if (IOTRAP(3)) {
-		if (gnvs && gnvs->smif)
-			io_trap_handler(gnvs->smif); // call function smif
-		return;
-	}
-
-	/* IOTRAP(2) currently unused
-	 * IOTRAP(1) currently unused */
-
-	/* IOTRAP(0) SMIC */
-	if (IOTRAP(0)) {
-		if (!(trap_cycle & (1 << 24))) { // It's a write
-			printk(BIOS_DEBUG, "SMI1 command\n");
-			data = RCBA32(0x1e18);
-			data &= mask;
-			// if (smi1)
-			//	southbridge_smi_command(data);
-			// return;
-		}
-		// Fall through to debug
-	}
-
-	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
-	for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
-	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
-	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
-	printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
-
-	if (!(trap_cycle & (1 << 24))) {
-		/* Write Cycle */
-		data = RCBA32(0x1e18);
-		printk(BIOS_DEBUG, "  iotrap written data = 0x%08x\n", data);
-	}
-#endif
-#undef IOTRAP
-}
-
 typedef void (*smi_handler_t)(void);
 
 smi_handler_t southbridge_smi[32] = {
@@ -562,7 +480,7 @@ smi_handler_t southbridge_smi[32] = {
 	NULL,			  // [18] INTEL_USB2_STS
 	NULL,			  // [19] reserved
 	NULL,			  // [20] PCI_EXP_SMI_STS
-	southbridge_smi_monitor,  // [21] MONITOR_STS
+	NULL,			  // [21] MONITOR_STS
 	NULL,			  // [22] reserved
 	NULL,			  // [23] reserved
 	NULL,			  // [24] reserved