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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-28 19:59:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:11:47 +0000
commit2f2191a3d0876fb90ab0c5f09e1c802b0a89b83e (patch)
treed6223becffbc16b567b319c1af84c01e00423420 /src/southbridge/intel/i82801dx/usb.c
parent5ac723e5a4a22bc9a08098cd59de5026b18d362d (diff)
downloadcoreboot-2f2191a3d0876fb90ab0c5f09e1c802b0a89b83e.tar.xz
sb/intel/i82801dx: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Ie27054ded47b91a27036b5b4a21ab69b387239dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801dx/usb.c')
-rw-r--r--src/southbridge/intel/i82801dx/usb.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c
index 696b55977a..2abfa8a34f 100644
--- a/src/southbridge/intel/i82801dx/usb.c
+++ b/src/southbridge/intel/i82801dx/usb.c
@@ -9,11 +9,8 @@
static void usb_init(struct device *dev)
{
- u32 cmd;
printk(BIOS_DEBUG, "USB: Setting up controller.. ");
- cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
- cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
printk(BIOS_DEBUG, "done.\n");
}