sb/intel/*: Use common SMBus functions

All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.

This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.

Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

4 files changed, 5 insertions, 256 deletions

diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index 82db1c3752..35e597acbf 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -22,6 +22,8 @@ config SOUTHBRIDGE_INTEL_I82801DX
 	select HAVE_HARD_RESET
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG
+	select SOUTHBRIDGE_INTEL_COMMON
+	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 
 if SOUTHBRIDGE_INTEL_I82801DX
 
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index 5bf87d8e91..fabb58b55b 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -17,6 +17,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
+#include <southbridge/intel/common/smbus.h>
 
 #include "i82801dx.h"
 
@@ -37,143 +38,7 @@ void enable_smbus(void)
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 }
 
-static inline void smbus_delay(void)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
-	outb(0x80, 0x80);
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
-
-static int smbus_wait_until_active(void)
-{
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		smbus_delay();
-		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ((val & 1)) {
-			break;
-		}
-	} while (--loops);
-	return loops ? 0 : -4;
-}
-
-static int smbus_wait_until_ready(void)
-{
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		smbus_delay();
-		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ((val & 1) == 0) {
-			break;
-		}
-		if (loops == (SMBUS_TIMEOUT / 2)) {
-			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
-			     SMBUS_IO_BASE + SMBHSTSTAT);
-		}
-	} while (--loops);
-	return loops ? 0 : -2;
-}
-
-static int smbus_wait_until_done(void)
-{
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		smbus_delay();
-
-		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ((val & 1) == 0) {
-			break;
-		}
-		if ((val & ~((1 << 6) | (1 << 0))) != 0) {
-			break;
-		}
-	} while (--loops);
-	return loops ? 0 : -3;
-}
-
-int smbus_read_byte(unsigned device, unsigned address)
-{
-	unsigned char global_status_register;
-	unsigned char byte;
-
-	/* printk(BIOS_ERR, "smbus_read_byte\n"); */
-	if (smbus_wait_until_ready() < 0) {
-		printk(BIOS_ERR, "SMBUS not ready (-2)\n");
-		return -2;
-	}
-
-	/* setup transaction */
-	/* disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
-	/* set the command/address... */
-	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
-	     SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
-	/* clear the data byte... */
-	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
-
-	/* start a byte read, with interrupts disabled */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
-	     SMBUS_IO_BASE + SMBHSTCTL);
-	/* poll for it to start */
-	if (smbus_wait_until_active() < 0) {
-		printk(BIOS_ERR, "SMBUS not active (-4)\n");
-		return -4;
-	}
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done() < 0) {
-		printk(BIOS_ERR, "SMBUS not completed (-3)\n");
-		return -3;
-	}
-
-	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6);	/* Ignore the In Use Status... */
-
-	/* read results of transaction */
-	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
-
-	if (global_status_register != 2) {
-		//printk(BIOS_SPEW, "%s: no device (%02x, %02x)\n", __func__, device, address);
-		return -1;
-	}
-	//printk(BIOS_DEBUG, "%s: %02x@%02x = %02x\n", __func__, device, address, byte);
-	return byte;
-}
-
-#if 0
-static void smbus_write_byte(unsigned device, unsigned address,
-			     unsigned char val)
-{
-	if (smbus_wait_until_ready() < 0) {
-		return;
-	}
-
-	/* by LYH */
-	outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT);
-	/* set the device I'm talking too */
-	outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
-
-	/* data to send */
-	outb(val, SMBUS_IO_BASE + SMBHSTDAT);
-
-	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-
-	/* start the command */
-	outb(0xa, SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* poll for transaction completion */
-	smbus_wait_until_done();
-	return;
-}
-#endif
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 3ab0fda8b2..14ca28f9aa 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -116,23 +116,6 @@ int smbus_read_byte(unsigned device, unsigned address);
 
 #define SMBUS_IO_BASE 0x1000
 
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL  0x2
-#define SMBHSTCMD  0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT  0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100*1000)
-
 #define PM1_STS		0x00
 #define   WAK_STS	(1 << 15)
 #define   PCIEXPWAK_STS	(1 << 14)
diff --git a/src/southbridge/intel/i82801dx/smbus.c b/src/southbridge/intel/i82801dx/smbus.c
deleted file mode 100644
index 441b45a98d..0000000000
--- a/src/southbridge/intel/i82801dx/smbus.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "i82801dx.h"
-#include <smbus.h>
-#include <pci.h>
-#include <arch/io.h>
-
-#define PM_BUS 0
-#define PM_DEVFN PCI_DEVFN(0x1f,3)
-
-void smbus_enable(void)
-{
-	unsigned char byte;
-	/* iobase addr */
-	pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1);
-	/* smbus enable */
-	pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1);
-	/* iospace enable */
-	pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
-
-	/* Disable interrupt generation */
-	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
-}
-
-void smbus_setup(void)
-{
-	outb(0, SMBUS_IO_BASE + SMBHSTSTAT);
-}
-
-static void smbus_wait_until_ready(void)
-{
-	while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
-		/* nop */
-	}
-}
-
-static void smbus_wait_until_done(void)
-{
-	unsigned char byte;
-	do {
-		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-	while ((byte & 1) == 1);
-	while ((byte & ~1) == 0) {
-		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-}
-
-int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
-{
-	unsigned char host_status_register;
-	unsigned char byte;
-
-	smbus_wait_until_ready();
-
-	/* setup transaction */
-	/* disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
-	/* set the command/address... */
-	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
-	     SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
-	/* clear the data byte... */
-	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
-
-	/* start the command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
-	     SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* poll for transaction completion */
-	smbus_wait_until_done();
-
-	host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-
-	/* read results of transaction */
-	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
-
-	*result = byte;
-	return host_status_register != 0x02;
-}