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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 01:02:28 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-20 17:04:46 +0000 |
| commit | b21bffae0ce5dee5d316ad544ccc6dedbc4475a1 (patch) | |
| tree | 5affe6f49cf0c7b7cb5b95d6cd5dd928d624dd8b /src/southbridge/intel/i82801dx | |
| parent | 65e5b100e2133a305ba1f471a23d75dc37a2224d (diff) | |
| download | coreboot-b21bffae0ce5dee5d316ad544ccc6dedbc4475a1.tar.xz | |
sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE
Make it default to 0x400, which is what the touched southbridges use.
Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801dx')
| -rw-r--r-- | src/southbridge/intel/i82801dx/early_smbus.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx.h | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 6649c33b8b..fc225b0466 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -12,7 +12,7 @@ void i82801dx_early_init(void) uintptr_t smbus_base(void) { - return SMBUS_IO_BASE; + return CONFIG_FIXED_SMBUS_IO_BASE; } int smbus_enable_iobar(uintptr_t base) diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index cf852740f9..d5790ae13b 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -94,8 +94,6 @@ void aseg_smm_lock(void); #define RTC_FAILED (1 <<2) -#define SMBUS_IO_BASE 0x400 - #define PM1_STS 0x00 #define WAK_STS (1 << 15) #define PCIEXPWAK_STS (1 << 14) |