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authorStefan Reinauer <stepan@openbios.org>2006-04-06 21:40:36 +0000
committerStefan Reinauer <stepan@openbios.org>2006-04-06 21:40:36 +0000
commit84e4bf69c7f0b6b4cf685fe0d6abf6ec93b2eff5 (patch)
tree716c33a7500dba12b30b3306656afd75824a5266 /src/southbridge/intel/i82801er/i82801er.c
parent966d0e6d70b20b6d14e265d59aaad37ce84d2ddb (diff)
downloadcoreboot-84e4bf69c7f0b6b4cf685fe0d6abf6ec93b2eff5.tar.xz
interesting behavior, i thought svn could do moves.
the result should be ok though.. the purpose is dropping the old i82801er southbridge code and using the ich5r code instead because its the same chip but the code looks more solid and is used by many more systems. Some of the old i82801er features have been ported (like hpet enable) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801er/i82801er.c')
-rw-r--r--src/southbridge/intel/i82801er/i82801er.c48
1 files changed, 48 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801er/i82801er.c b/src/southbridge/intel/i82801er/i82801er.c
new file mode 100644
index 0000000000..5e38ac3acb
--- /dev/null
+++ b/src/southbridge/intel/i82801er/i82801er.c
@@ -0,0 +1,48 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801er.h"
+
+void i82801er_enable(device_t dev)
+{
+ device_t lpc_dev;
+ unsigned index = 0;
+ uint16_t reg_old, reg;
+
+ /* See if we are behind the i82801er pci bridge */
+ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
+ if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
+ index = dev->path.u.pci.devfn & 7;
+ }
+ else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
+ index = (dev->path.u.pci.devfn & 7) +8;
+ }
+ if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
+ return;
+ }
+ if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
+ (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_ISA)) {
+ uint32_t id;
+ id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
+ if (id != (PCI_VENDOR_ID_INTEL |
+ (PCI_DEVICE_ID_INTEL_82801ER_ISA << 16))) {
+ return;
+ }
+ }
+
+ reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
+ reg &= ~(1 << index);
+ if (!dev->enabled) {
+ reg |= (1 << index);
+ }
+ if (reg != reg_old) {
+ pci_write_config16(lpc_dev, 0xf2, reg);
+ }
+
+}
+
+struct chip_operations southbridge_intel_i82801er_ops = {
+ CHIP_NAME("Intel 82801ER Southbridge")
+ .enable_dev = i82801er_enable,
+};