diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-16 18:31:34 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-16 18:31:34 +0000 |
| commit | 0401bd89b6e7105ca597a221fdbe2a8b75c35296 (patch) | |
| tree | ec342f9dcaae2619bcb06a57789a07328402ea71 /src/southbridge/intel/i82801er | |
| parent | 9fe4d797a37671a65053add3f7cca27397db0b9b (diff) | |
| download | coreboot-0401bd89b6e7105ca597a221fdbe2a8b75c35296.tar.xz | |
coreboot has 13 instances of IOAPIC setup distributed across a lot
of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801er')
| -rw-r--r-- | src/southbridge/intel/i82801er/i82801er_lpc.c | 48 |
1 files changed, 2 insertions, 46 deletions
diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c index 943356c2c1..357e181a9d 100644 --- a/src/southbridge/intel/i82801er/i82801er_lpc.c +++ b/src/southbridge/intel/i82801er/i82801er_lpc.c @@ -9,6 +9,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801er.h" #define ACPI_BAR 0x40 @@ -22,51 +23,6 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -#define ALL (0xff << 24) -#define NONE (0) -#define DISABLED (1 << 16) -#define ENABLED (0 << 16) -#define TRIGGER_EDGE (0 << 15) -#define TRIGGER_LEVEL (1 << 15) -#define POLARITY_HIGH (0 << 13) -#define POLARITY_LOW (1 << 13) -#define PHYSICAL_DEST (0 << 11) -#define LOGICAL_DEST (1 << 11) -#define ExtINT (7 << 8) -#define NMI (4 << 8) -#define SMI (2 << 8) -#define INT (1 << 8) - -static void setup_ioapic(void) -{ - int i; - unsigned long value_low, value_high; - unsigned long ioapic_base = 0xfec00000; - volatile unsigned long *l; - unsigned interrupts; - - l = (unsigned long *) ioapic_base; - - l[0] = 0x01; - interrupts = (l[04] >> 16) & 0xff; - for (i = 0; i < interrupts; i++) { - l[0] = (i * 2) + 0x10; - l[4] = DISABLED; - value_low = l[4]; - l[0] = (i * 2) + 0x11; - l[4] = NONE; /* Should this be an address? */ - value_high = l[4]; - if (value_low == 0xffffffff) { - printk_warning("IO APIC not responding.\n"); - return; - } - } - - /* Put the ioapic in virtual wire mode */ - l[0] = 0 + 0x10; - l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; -} - #define SERIRQ_CNTL 0x64 static void i82801er_enable_serial_irqs(device_t dev) { @@ -292,7 +248,7 @@ static void lpc_init(struct device *dev) value = pci_read_config32(dev, 0xd4); value |= (1<<1); pci_write_config32(dev, 0xd4, value); - setup_ioapic(); + setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. i82801er_enable_serial_irqs(dev); |