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| author | Myles Watson <mylesgw@gmail.com> | 2009-07-02 18:56:24 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-07-02 18:56:24 +0000 |
| commit | 29cc9eda2021a87396ef31a6fc81daff6fd1be7a (patch) | |
| tree | d3dfa07ca85547c77c5d07825fc8afcc19489076 /src/southbridge/intel/i82801er | |
| parent | 2468331952bae0abdc4d76dbe6cf26f05b7825e5 (diff) | |
| download | coreboot-29cc9eda2021a87396ef31a6fc81daff6fd1be7a.tar.xz | |
Move the v3 resource allocator to v2.
Major changes:
1. Separate resource allocation into:
A. Read Resources
B. Avoid fixed resources (constrain limits)
C. Allocate resources
D. Set resources
Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources. All fixed resources will end up outside (above or below)
the allocated resources.
Domains usually start with base = 0 and limit = 2^address_bits - 1.
I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources. Some platforms may want to change that, but I didn't
want to break anyone's board.
Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801er')
| -rw-r--r-- | src/southbridge/intel/i82801er/i82801er_lpc.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c index fa89469693..943356c2c1 100644 --- a/src/southbridge/intel/i82801er/i82801er_lpc.c +++ b/src/southbridge/intel/i82801er/i82801er_lpc.c @@ -334,7 +334,7 @@ static void i82801er_lpc_read_resources(device_t dev) { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); /* Add the ACPI BAR */ @@ -343,12 +343,23 @@ static void i82801er_lpc_read_resources(device_t dev) /* Add the GPIO BAR */ res = pci_get_resource(dev, GPIO_BAR); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801er_lpc_enable_resources(device_t dev) |