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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
| commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
| tree | 001fba539061f4075699fc98e02b3153259477e9 /src/southbridge/intel/i82801gx/Makefile.inc | |
| parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
| download | coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.xz | |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/i82801gx/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 2e9d31a3e8..31264295ad 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -15,6 +15,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) +bootblock-y += early_init.c bootblock-y += bootblock_gcc.c ramstage-y += i82801gx.c @@ -34,6 +35,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c +romstage-y += early_init.c romstage-y += early_smbus.c romstage-y += early_cir.c |