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| author | Stefan Reinauer <stepan@coresystems.de> | 2009-07-21 21:50:34 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-07-21 21:50:34 +0000 |
| commit | 573f7d40be086b35b25d242818ae0e9c26d05022 (patch) | |
| tree | 831bf36c8294b2dd1362af4e6de3b3f0df0fff50 /src/southbridge/intel/i82801gx/acpi/ich7_pci.asl | |
| parent | 71a3d96bc487f66c84ac869a1215b8a4a4499bf2 (diff) | |
| download | coreboot-573f7d40be086b35b25d242818ae0e9c26d05022.tar.xz | |
Intel ICH7 updates
- code restructuring (move ich7 out of i945)
- ACPI fixes
- major SMI handler updates
- make sure SMBus lives where we expect it
- try to get usb debug working
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801gx/acpi/ich7_pci.asl')
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7_pci.asl | 60 |
1 files changed, 19 insertions, 41 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl index bcdf084e37..775a34dfe8 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl @@ -43,6 +43,24 @@ Device (PCIB) Name (_PRW, Package(){ 11, 4 }) } + Device (SLT6) + { + Name (_ADR, 0x00050000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (LANC) + { + Name (_ADR, 0x00080000) + Name (_PRW, Package(){ 11, 3 }) + } + + Device (LANR) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package(){ 11, 3 }) + } + // TODO: How many slots, where? // PCI Interrupt Routing. @@ -52,47 +70,7 @@ Device (PCIB) Method (_PRT) { - If (PICM) { - Return (Package() { - // PCI Slot 1 routes FGHE - Package() { 0x0000ffff, 0, 0, 16}, /* Firewire */ - Package() { 0x0000ffff, 1, 0, 22}, - Package() { 0x0000ffff, 2, 0, 23}, - Package() { 0x0000ffff, 3, 0, 20}, - - // PCI Slot 2 routes GFEH (but is EFGH now, because that actually works) - Package() { 0x0001ffff, 0, 0, 20}, - Package() { 0x0001ffff, 1, 0, 21}, - Package() { 0x0001ffff, 2, 0, 22}, - Package() { 0x0001ffff, 3, 0, 23}, - - // PCI Slot 3 routes CDBA - Package() { 0x0002ffff, 0, 0, 18}, - Package() { 0x0002ffff, 1, 0, 19}, - Package() { 0x0002ffff, 2, 0, 17}, - Package() { 0x0002ffff, 3, 0, 16} - }) - } Else { - Return (Package() { - // PCI Slot 1 routes FGHE - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, - - // PCI Slot 2 routes GFEH - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, - Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, - Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, - Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, - - // PCI Slot 3 routes CDBA - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, - Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, - Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, - Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, - }) - } + Include ("acpi/ich7_pci_irqs.asl") } } |