Intel ICH7 updates

- code restructuring (move ich7 out of i945)
- ACPI fixes 
- major SMI handler updates
- make sure SMBus lives where we expect it
- try to get usb debug working 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 344 insertions, 66 deletions

diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
new file mode 100644
index 0000000000..368e90679f
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Global Variables */
+
+Name(\PICM, 0)		// IOAPIC/8259
+Name(\DSEN, 1)		// Display Output Switching Enable
+
+/* Global ACPI memory region. This region is used for passing information 
+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
+ * Since we don't know where this will end up in memory at ACPI compile time,
+ * we have to fix it up in coreboot's ACPI creation phase.
+ */
+
+
+OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x100)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Miscellaneous */
+	Offset (0x00),
+	OSYS,	16,	// 0x00 - Operating System
+	SMIF,	 8,	// 0x02 - SMI function
+	PRM0,	 8,	// 0x03 - SMI function parameter
+	PRM1,	 8,	// 0x04 - SMI function parameter
+	SCIF,	 8,	// 0x05 - SCI function
+	PRM2,	 8,	// 0x06 - SCI function parameter
+	PRM3,	 8,	// 0x07 - SCI function parameter
+	LCKF,	 8,	// 0x08 - Global Lock function for EC
+	PRM4,	 8,	// 0x09 - Lock function parameter
+	PRM5,	 8,	// 0x0a - Lock function parameter
+	P80D,	32,	// 0x0b - Debug port (IO 0x80) value
+	LIDS,	 8,	// 0x0f - LID state (open = 1)
+	PWRS,	 8,	// 0x10 - Power State (AC = 1)
+	DBGS,	 8,	// 0x11 - Debug State
+	LINX,    8,	// 0x12 - Linux OS
+	DCKN,	 8,	// 0x13 - PCIe docking state
+	/* Thermal policy */
+	Offset (0x14),
+	ACTT,	 8,	// 0x14 - active trip point
+	PSVT,	 8,	// 0x15 - passive trip point
+	TC1V,	 8,	// 0x16 - passive trip point TC1
+	TC2V,	 8,	// 0x17 - passive trip point TC2
+	TSPV,	 8,	// 0x18 - passive trip point TSP
+	CRTT,	 8,	// 0x19 - critical trip point
+	DTSE,	 8,	// 0x1a - Digital Thermal Sensor enable
+	DTS1,	 8,	// 0x1b - DT sensor 1
+	DTS2,	 8,	// 0x1c - DT sensor 2
+	/* Battery Support */
+	Offset (0x1e),
+	BNUM,	 8,	// 0x1e - number of batteries
+	B0SC,	 8,	// 0x1f - BAT0 stored capacity
+	B1SC,	 8,	// 0x20 - BAT1 stored capacity
+	B2SC,	 8,	// 0x21 - BAT2 stored capacity
+	B0SS,	 8,	// 0x22 - BAT0 stored status
+	B1SS,	 8,	// 0x23 - BAT1 stored status
+	B2SS,	 8,	// 0x24 - BAT2 stored status
+	/* Processor Identification */
+	Offset (0x28),
+	APIC,	 8,	// 0x28 - APIC Enabled by coreboot
+	MPEN,	 8,	// 0x29 - Multi Processor Enable
+	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
+	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
+	PPCM,	 8,	// 0x2c - Max. PPC state
+	/* Super I/O & CMOS config */
+	Offset (0x32),
+	NATP,	 8,	// 0x32 - ...
+	/* Integrated Graphics Device */
+	Offset (0x3c),
+	IGDS,	 8,	// 0x3c - IGD state (primary = 1)
+	TLST,	 8,	// 0x3d - Display Toggle List pointer
+	CADL,	 8,	// 0x3e - Currently Attached Devices List
+	PADL,	 8,	// 0x3f - Previously Attached Devices List
+	CSTE,	16,	// 0x40 - Current display state
+	NSTE,	16,	// 0x42 - Next display state
+	SSTE,	16,	// 0x44 - Set display state
+	Offset (0x46),
+	NDID,	 8,	// 0x46 - Number of Device IDs
+	DID1,	32,	// 0x47 - Device ID 1
+	DID2,	32,	// 0x4b - Device ID 2
+	DID3,	32,	// 0x4f - Device ID 3
+	DID4,	32,	// 0x53 - Device ID 4
+	DID5,	32,	// 0x57 - Device ID 5
+	/* Backlight Control */
+	Offset (0x64),
+	BLCS,	 8,	// 0x64 - Backlight control possible?
+	BRTL,	 8,	// 0x65 - Brightness Level
+	ODDS,	 8,	// 0x66
+	/* Ambient Light Sensors */
+	Offset (0x6e),
+	ALSE,	 8,	// 0x6e - ALS enable
+	ALAF,	 8,	// 0x6f - Ambient light adjustment factor
+	LLOW,	 8,	// 0x70 - LUX Low
+	LHIH,	 8,	// 0x71 - LUX High
+	/* EMA */
+	Offset (0x78),
+	EMAE,	 8,	// 0x78 - EMA enable
+	EMAP,	16,	// 0x79 - EMA pointer
+	EMAL,	16,	// 0x7b - EMA length
+	/* MEF */
+	Offset (0x82),
+	MEFE,	 8,	// 0x82 - MEF enable
+	/* TPM support */
+	Offset (0x8c),
+	TPMP,	 8,	// 0x8c - TPM
+	TPME,	 8,	// 0x8d - TPM enable
+	/* SATA */
+	Offset (0x96),
+	GTF0,	56,	// 0x96 - GTF task file buffer for port 0
+	GTF1,	56,	// 0x9d - GTF task file buffer for port 1
+	GTF2,	56,	// 0xa4 - GTF task file buffer for port 2
+	IDEM,	 8,	// 0xab - IDE mode (compatible / enhanced)
+	IDET,	 8,	// 0xac - IDE
+	/* IGD OpRegion */
+	Offset (0xb4),
+	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
+	IBTT,	 8,	// 0xb8 - IGD boot panel device
+	IPAT,	 8,	// 0xb9 - IGD panel type cmos option
+	ITVF,	 8,	// 0xba - IGD TV format cmos option
+	ITVM,	 8,	// 0xbb - IGD TV minor format option
+	IPSC,	 8,	// 0xbc - IGD panel scaling
+	IBLC,	 8,	// 0xbd - IGD BLC config
+	IBIA,	 8,	// 0xbe - IGD BIA config
+	ISSC,	 8,	// 0xbf - IGD SSC config
+	I409,	 8,	// 0xc0 - IGD 0409 modified settings
+	I509,	 8,	// 0xc1 - IGD 0509 modified settings
+	I609,	 8,	// 0xc2 - IGD 0609 modified settings
+	I709,	 8,	// 0xc3 - IGD 0709 modified settings
+	IDMM,	 8,	// 0xc4 - IGD DVMT Mode
+	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
+	IF1E,	 8,	// 0xc6 - IGD function 1 enable
+	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
+	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
+	NXD2,	32,	// 0xcc - IGD _DGS next DID2
+	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
+	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
+	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
+	NXD6,	32,	// 0xdc - IGD _DGS next DID6
+	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
+	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
+	/* Mainboard Specific (TODO move elsewhere) */
+	Offset (0xf0),
+	DOCK,	 8,	// 0xf0 - Docking Status
+}
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index 2e7233d948..dd3bc87e2f 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -92,7 +92,8 @@ Scope(\)
 		Offset(0x38),	// GPIO Level 2
 		, 5,
 		GP37, 1,	// PATA_PWR_EN
-		, 2,
+		GP38, 1,	// Battery / Power (?)
+		GP39, 1,	// ??
 		GL05, 8,
 		GL06, 8,
 		GL07, 8
@@ -100,7 +101,7 @@ Scope(\)
 
 
 	// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
-	OperationRegion(RCRB, SystemMemory, 0xfff1000, 0x4000)
+	OperationRegion(RCRB, SystemMemory, 0xfed1c000, 0x4000)
 	Field(RCRB, DWordAcc, Lock, Preserve)
 	{
 		Offset(0x0000), // Backbone
@@ -111,12 +112,22 @@ Scope(\)
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
-		, 1,
+		, 1,		// Reserved
 		PATD, 1,	// PATA disable
 		SATD, 1,	// SATA disable
 		SMBD, 1,	// SMBUS disable
 		HDAD, 1,	// Azalia disable
-		, 11,		// ... FIXME
+		A97D, 1,	// AC'97 disable
+		M97D, 1,	// AC'97 disable
+		ILND, 1,	// Internal LAN disable
+		US1D, 1,	// UHCI #1 disable
+		US2D, 1,	// UHCI #2 disable
+		US3D, 1,	// UHCI #3 disable
+		US4D, 1,	// UHCI #4 disable
+		, 2,		// Reserved
+		LPBD, 1,	// LPC bridge disable
+		EHCD, 1,	// EHCI disable
+		Offset(0x341a), // FD Root Ports
 		RP1D, 1,	// Root Port 1 disable
 		RP2D, 1,	// Root Port 2 disable
 		RP3D, 1,	// Root Port 3 disable
@@ -139,6 +150,9 @@ Include ("../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl")
 // PCI Bridge
 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl")
 
+// AC97 Audio and Modem
+Include ("../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl")
+
 // LPC Bridge
 Include ("../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl")
 
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl b/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
new file mode 100644
index 0000000000..7f76ccc786
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel i82801G AC'97 Audio and Modem */
+
+// Intel AC'97 Audio 0:1e.2
+
+Device (AUD0)
+{
+	Name (_ADR, 0x001e0002)
+}
+
+// Intel AC'97 Modem 0:1e.3
+
+Device (MODM)
+{
+	Name (_ADR, 0x001e0003)
+	
+	Name (_PRW, Package(){ 5, 4 })
+}
+
+
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl b/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
index 01ae8c58ec..5b8b386c39 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
@@ -27,6 +27,10 @@ Device (HDEF)
 {
 	Name (_ADR, 0x001b0000)
 
-	Name (_PRW, Package(){ 13, 4 })
+	// Power Resources for Wake
+	Name (_PRW, Package(){ 
+		5,  // Bit 5 of GPE
+		4   // Can wake from S4 state.
+	})
 }
 
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl b/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
index 80ba6e73bf..d5705396ce 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
@@ -68,7 +68,7 @@ Device (LPCB)
 		})
 	}
 
-	Device (FWHD)		// Firmware Hub
+	Device (FWH)		// Firmware Hub
 	{
 		Name (_HID, EISAID("INT0800"))
 		Name (_CRS, ResourceTemplate()
@@ -80,7 +80,7 @@ Device (LPCB)
 	Device (HPET)
 	{
 		Name (_HID, EISAID("PNP0103"))
-		Name (_CID, EISAID("PNP0C01"))
+		Name (_CID, 0x010CD041)
 
 		Name(BUF0, ResourceTemplate()
 		{
@@ -92,18 +92,32 @@ Device (LPCB)
 			If (HPTE) {
 				// Note: Ancient versions of Windows don't want
 				// to see the HPET in order to work right
-				// Return (0xb)	// Enable and don't show device
-
-				Return (0xf)	// Enable and show device
+				If (LGreaterEqual(OSYS, 2001)) {
+					Return (0xf)	// Enable and show device
+				} Else {
+					Return (0xb)	// Enable and don't show device
+				}
 			}
 
 			Return (0x0)	// Not enabled, don't show.
 		}
 
-		Method (_CRS, 0, Serialized)
+		Method (_CRS, 0, Serialized) // Current resources
 		{
-			// Here we could do crazy stuff like move the HPET. Why
-			// should we?
+			If (HPTE) {
+				CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
+				If (Lequal(HPAS, 1)) {
+					Store(0xfed01000, HPT0)
+				}
+
+				If (Lequal(HPAS, 2)) {
+					Store(0xfed02000, HPT0)
+				}
+
+				If (Lequal(HPAS, 3)) {
+					Store(0xfed03000, HPT0)
+				}
+			}
 
 			Return (BUF0)
 		}
@@ -130,7 +144,7 @@ Device (LPCB)
 			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
 			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
 			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
-			IO (Decode16, 0x4d0, 0x4b0, 0x01, 0x02)
+			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
 			IRQNoFlags () { 2 }
 		})
 	}
@@ -145,7 +159,7 @@ Device (LPCB)
 		})
 	}
 
-	Device(MISC)	// Various other devices
+	Device(LDRC)	// LPC device: Resource consumption
 	{
 		Name (_HID, EISAID("PNP0C02"))
 		Name (_UID, 2)
@@ -153,18 +167,18 @@ Device (LPCB)
 		{
 			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02)		// First SuperIO
 			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02)		// Second SuperIO
-			IO (Decode16, 0x61, 0x61, 0x1, 0x1)		// NMI Status
-			IO (Decode16, 0x63, 0x63, 0x1, 0x1)		// CPU Reserved
-			IO (Decode16, 0x65, 0x65, 0x1, 0x1)		// CPU Reserved
-			IO (Decode16, 0x67, 0x67, 0x1, 0x1)		// CPU Reserved
-			IO (Decode16, 0x80, 0x80, 0x1, 0x1)		// Port 80 Post
-			IO (Decode16, 0x92, 0x92, 0x1, 0x1)		// CPU Reserved
+			IO (Decode16, 0x61, 0x61, 0x1, 0x01)		// NMI Status
+			IO (Decode16, 0x63, 0x63, 0x1, 0x01)		// CPU Reserved
+			IO (Decode16, 0x65, 0x65, 0x1, 0x01)		// CPU Reserved
+			IO (Decode16, 0x67, 0x67, 0x1, 0x01)		// CPU Reserved
+			IO (Decode16, 0x80, 0x80, 0x1, 0x01)		// Port 80 Post
+			IO (Decode16, 0x92, 0x92, 0x1, 0x01)		// CPU Reserved
 			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02)		// SWSMI
-			IO (Decode16, 0x680, 0x680, 0x1, 0x70)		// IO ???
+			// IO (Decode16, 0x680, 0x680, 0x1, 0x70)	// IO ???
 			IO (Decode16, 0x800, 0x800, 0x1, 0x10)		// ACPI I/O trap
 			IO (Decode16, 0x0500, 0x0500, 0x1, 0x80)	// ICH7-M ACPI
-			IO (Decode16, 0x1180, 0x1180, 0x1, 0x40)	// ICH7-M GPIO
-			IO (Decode16, 0x1640, 0x1640, 0x1, 0x10)	// IO ???
+			IO (Decode16, 0x0480, 0x0480, 0x1, 0x40)	// ICH7-M GPIO
+			// IO (Decode16, 0x1640, 0x1640, 0x1, 0x10)	// IO ???
 		})
 	}
 
@@ -194,12 +208,19 @@ Device (LPCB)
 	Device (PS2K)		// Keyboard
 	{
 		Name(_HID, EISAID("PNP0303"))
+		Name(_CID, EISAID("PNP030B"))
+
 		Name(_CRS, ResourceTemplate()
 		{
 			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
 			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
 			IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1
 		})
+
+		Method (_STA, 0)
+		{
+			Return (0xf)
+		}
 	}
 
 	Device (PS2M)		// Mouse
@@ -209,5 +230,36 @@ Device (LPCB)
 		{
 			IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12
 		})
+
+		Method(_STA, 0)
+		{
+			Return (0xf)
+		}
+	}
+
+	Device (FDC0)		// Floppy controller
+	{
+		Name (_HID, EisaId ("PNP0700"))
+		Method (_STA, 0, NotSerialized)
+		{
+			Return (0x0f) // FIXME
+		}
+
+		Name(_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
+			IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
+			IRQNoFlags () {6}
+			DMA (Compatibility, NotBusMaster, Transfer8) {2}
+		})
+
+		Name(_PRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
+			IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
+			IRQNoFlags () {6}
+			DMA (Compatibility, NotBusMaster, Transfer8) {2}
+		})
+
 	}
 }
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
index bcdf084e37..775a34dfe8 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
@@ -43,6 +43,24 @@ Device (PCIB)
 		Name (_PRW, Package(){ 11, 4 })
 	}
 
+	Device (SLT6)
+	{
+		Name (_ADR, 0x00050000)
+		Name (_PRW, Package(){ 11, 4 })
+	}
+
+	Device (LANC)
+	{
+		Name (_ADR, 0x00080000)
+		Name (_PRW, Package(){ 11, 3 })
+	}
+
+	Device (LANR)
+	{
+		Name (_ADR, 0x00000000)
+		Name (_PRW, Package(){ 11, 3 })
+	}
+
 	// TODO: How many slots, where?
 
 	// PCI Interrupt Routing.
@@ -52,47 +70,7 @@ Device (PCIB)
 
 	Method (_PRT)
 	{
-		If (PICM) {
-			Return (Package() {
-				// PCI Slot 1 routes FGHE
-				Package() { 0x0000ffff, 0, 0, 16}, /* Firewire */
-				Package() { 0x0000ffff, 1, 0, 22},
-				Package() { 0x0000ffff, 2, 0, 23},
-				Package() { 0x0000ffff, 3, 0, 20},
-
-				// PCI Slot 2 routes GFEH (but is EFGH now, because that actually works)
-				Package() { 0x0001ffff, 0, 0, 20},
-				Package() { 0x0001ffff, 1, 0, 21},
-				Package() { 0x0001ffff, 2, 0, 22},
-				Package() { 0x0001ffff, 3, 0, 23},
-
-				// PCI Slot 3 routes CDBA
-				Package() { 0x0002ffff, 0, 0, 18},
-				Package() { 0x0002ffff, 1, 0, 19},
-				Package() { 0x0002ffff, 2, 0, 17},
-				Package() { 0x0002ffff, 3, 0, 16}
-			})
-		} Else {
-			Return (Package() {
-				// PCI Slot 1 routes FGHE
-				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
-				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
-				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
-				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
-
-				// PCI Slot 2 routes GFEH
-				Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
-				Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
-				Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
-				Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
-
-				// PCI Slot 3 routes CDBA
-				Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
-				Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
-				Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
-				Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
-			})
-		}
+		Include ("acpi/ich7_pci_irqs.asl")
 	}
 
 }
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl b/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
index d0779b75c3..6b1009c24a 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
@@ -33,7 +33,8 @@ Device (SBUS)
 		I2CE,	1
 	}
 
-	OperationRegion (SMBI, SystemIO, 0x500, 0x20)
+	/*
+	OperationRegion (SMBI, SystemIO, 0x400, 0x20)
 	Field (SMBI, ByteAcc, NoLock, Preserve)
 	{
 		HSTS,	8,	// Host Status
@@ -236,6 +237,7 @@ Device (SBUS)
 
 		Return (0xffff)
 	}
+	*/
 
 	// Todo: Does anyone ever use these?
 	// Missing: Read / Write Word
diff --git a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl
new file mode 100644
index 0000000000..61595854b2
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name(\_S0, Package(4){0x0,0x0,0,0})
+Name(\_S1, Package(4){0x1,0x0,0,0})
+Name(\_S3, Package(4){0x5,0x0,0,0})
+Name(\_S4, Package(4){0x6,0x0,0,0})
+Name(\_S5, Package(4){0x7,0x0,0,0})
+