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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-26 08:52:10 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-10 18:22:04 +0200 |
| commit | 8aa7e839943560c57d0c39278bfcf3ae3eda29e0 (patch) | |
| tree | 2c6288236e047e20f3c1e75bd2a681b33d02733b /src/southbridge/intel/i82801gx/azalia.c | |
| parent | 9b143e1474f425b6d81bf6490d67baf26d03c437 (diff) | |
| download | coreboot-8aa7e839943560c57d0c39278bfcf3ae3eda29e0.tar.xz | |
intel/i945 intel/i82801gx: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3811
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/azalia.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/azalia.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index ad9faa5a9f..96e662c638 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -224,39 +224,35 @@ static void azalia_init(struct device *dev) u8 reg8; u32 reg32; -#if CONFIG_MMCONF_SUPPORT // ESD - reg32 = pci_mmio_read_config32(dev, 0x134); + reg32 = pci_read_config32(dev, 0x134); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x134, reg32); + pci_write_config32(dev, 0x134, reg32); // Link1 description - reg32 = pci_mmio_read_config32(dev, 0x140); + reg32 = pci_read_config32(dev, 0x140); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x140, reg32); + pci_write_config32(dev, 0x140, reg32); // Port VC0 Resource Control Register - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); // VCi traffic class - reg8 = pci_mmio_read_config8(dev, 0x44); + reg8 = pci_read_config8(dev, 0x44); reg8 |= (7 << 0); // TC7 - pci_mmio_write_config8(dev, 0x44, reg8); + pci_write_config8(dev, 0x44, reg8); // VCi Resource Control - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); reg32 |= (1 << 24); // VCi ID reg32 |= (0x80 << 0); // VCi map - pci_mmio_write_config32(dev, 0x120, reg32); -#else -#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT -#endif + pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); |