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authorVladimir Serbinenko <phcoder@gmail.com>2014-11-22 20:36:58 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-12-03 21:02:12 +0100
commit4aad743434516d6c96f1afe21dd00b631e2c3692 (patch)
treef895dcff92712dd51af55fae3d71feeceb644e1b /src/southbridge/intel/i82801gx/bootblock.c
parenta234f45601e6e85a5179ec9cc446f070b86f425b (diff)
downloadcoreboot-4aad743434516d6c96f1afe21dd00b631e2c3692.tar.xz
i82801gx: Enable upper CMOS in bootblock.
Otherwise checksum may not work correctly on early stages. For compatibility with old bootblocks also enable it early in romstage. Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/bootblock.c')
-rw-r--r--src/southbridge/intel/i82801gx/bootblock.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 7b4cd7d57f..d8e03b7639 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/tsc.h>
+#include "i82801gx.h"
static void store_initial_timestamp(void)
{
@@ -50,4 +51,10 @@ static void bootblock_southbridge_init(void)
store_initial_timestamp();
#endif
enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
}