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| author | Sven Schnelle <svens@stackframe.org> | 2011-10-23 16:35:01 +0200 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-10-25 19:20:34 +0200 |
| commit | 906f9ae784b8a593319c400cbcc5e555a29b4128 (patch) | |
| tree | 463270b06f0b8c73b36ec28290df3ece8ad8c224 /src/southbridge/intel/i82801gx/chip.h | |
| parent | 54600970417fee0e87d3059f6e6ac0a59d829066 (diff) | |
| download | coreboot-906f9ae784b8a593319c400cbcc5e555a29b4128.tar.xz | |
i82801gx: Add setting for C4onC3 mode
If this bit is set, ich7 will enter C4 mode if possible instead of
C3. See ich7 specification (LPC controller, Power management control
registers) for more details.
Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/i82801gx/chip.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 4aea26e347..b775d39ee8 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -68,6 +68,8 @@ struct southbridge_intel_i82801gx_config { uint32_t ide_enable_primary; uint32_t ide_enable_secondary; uint32_t sata_ahci; + + int c4onc3_enable:1; }; extern struct chip_operations southbridge_intel_i82801gx_ops; |