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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-20 01:44:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-17 14:53:08 +0000 |
| commit | e6e5ecb7e813fa151c558c739d5394dce0a2af8e (patch) | |
| tree | 5227024409ee0826db078d98aee3a61a1204c352 /src/southbridge/intel/i82801gx/chip.h | |
| parent | 7bbe3bb9f0caf518af89bc18b99cd9ac32ceff3f (diff) | |
| download | coreboot-e6e5ecb7e813fa151c558c739d5394dce0a2af8e.tar.xz | |
sb/intel/i82801gx: Implement PCIe coalescing
The implementation is a simplified version of the haswell/broadwell
code. This also adds a chip option to enable coalescing from the
devicetree.
Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801gx/chip.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 3a20ab1cb3..db27ef7097 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -68,6 +68,9 @@ struct southbridge_intel_i82801gx_config { uint32_t sata_ahci; uint32_t sata_ports_implemented; + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + int c4onc3_enable:1; int docking_supported:1; int p_cnt_throttling_supported:1; |