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authorArthur Heymans <arthur@aheymans.xyz>2019-11-09 14:19:04 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-12 18:22:57 +0000
commitfecf77770b8e68b9ef82021ca53c31db93736d93 (patch)
tree001fba539061f4075699fc98e02b3153259477e9 /src/southbridge/intel/i82801gx/chip.h
parent675cb9152e6704383cf402c55758ddea2c7a1e05 (diff)
downloadcoreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.xz
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/chip.h')
-rw-r--r--src/southbridge/intel/i82801gx/chip.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index 4e78c30db2..75b957573e 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -80,6 +80,12 @@ struct southbridge_intel_i82801gx_config {
int docking_supported:1;
int p_cnt_throttling_supported:1;
int c3_latency;
+
+ /* Additional LPC IO decode ranges */
+ uint32_t gen1_dec;
+ uint32_t gen2_dec;
+ uint32_t gen3_dec;
+ uint32_t gen4_dec;
};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */