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| author | Stefan Reinauer <stepan@coresystems.de> | 2008-10-29 04:46:52 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2008-10-29 04:46:52 +0000 |
| commit | debb11fc1fe5f5560015ab9905f1ccc2e08c73e0 (patch) | |
| tree | 9160cd3787a3213a38f5e9b9942360bcaf753f1a /src/southbridge/intel/i82801gx/chip.h | |
| parent | b70d1993a432af2a026c4cad0fa3dd3c5eca1ef7 (diff) | |
| download | coreboot-debb11fc1fe5f5560015ab9905f1ccc2e08c73e0.tar.xz | |
Support for the Intel ICH7 southbridge.
This includes an early SMI handler.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801gx/chip.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/chip.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h new file mode 100644 index 0000000000..755c317531 --- /dev/null +++ b/src/southbridge/intel/i82801gx/chip.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H + +struct southbridge_intel_i82801gx_config { + uint32_t ide_legacy_combined; + uint32_t ide_enable_primary; + uint32_t ide_enable_secondary; + uint32_t sata_ahci; +}; + +extern struct chip_operations southbridge_intel_i82801gx_ops; + +#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ |