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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
tree | 001fba539061f4075699fc98e02b3153259477e9 /src/southbridge/intel/i82801gx/early_init.c | |
parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
download | coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.xz |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/early_init.c')
-rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c new file mode 100644 index 0000000000..533aaefe14 --- /dev/null +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include "i82801gx.h" +#include "chip.h" + +void i82801gx_lpc_setup(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_i82801gx_config *config; + + /* Configure serial IRQs.*/ + pci_write_config8(d31f0, SERIRQ_CNTL, 0xd0); + /* + * Enable some common LPC IO ranges: + * - 0x2e/0x2f, 0x4e/0x4f often SuperIO + * - 0x60/0x64, 0x62/0x66 often KBC/EC + * - 0x3f0-0x3f5/0x3f7 FDD + * - 0x378-0x37f and 0x778-0x77f LPT + * - 0x2f8-0x2ff COMB + * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL + */ + pci_write_config16(d31f0, LPC_IO_DEC, 0x0010); + pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + + /* Set up generic decode ranges */ + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec); + pci_write_config32(d31f0, GEN2_DEC, config->gen2_dec); + pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec); + pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec); +} |