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authorStefan Reinauer <stepan@coresystems.de>2008-10-29 04:46:52 +0000
committerStefan Reinauer <stepan@openbios.org>2008-10-29 04:46:52 +0000
commitdebb11fc1fe5f5560015ab9905f1ccc2e08c73e0 (patch)
tree9160cd3787a3213a38f5e9b9942360bcaf753f1a /src/southbridge/intel/i82801gx/i82801gx.c
parentb70d1993a432af2a026c4cad0fa3dd3c5eca1ef7 (diff)
downloadcoreboot-debb11fc1fe5f5560015ab9905f1ccc2e08c73e0.tar.xz
Support for the Intel ICH7 southbridge.
This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx.c')
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
new file mode 100644
index 0000000000..6daa57dbe3
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "i82801gx.h"
+
+void i82801gx_enable(device_t dev)
+{
+
+}
+
+struct chip_operations southbridge_intel_i82801gx_ops = {
+ CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge")
+ .enable_dev = i82801gx_enable,
+};