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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-22 14:42:18 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 09:35:58 +0000 |
commit | 3664647a25f31a26993433dcb6754484f58a9a62 (patch) | |
tree | 03ae06cb94e49993c5388f1197a30f30cb2a5be0 /src/southbridge/intel/i82801gx/i82801gx.h | |
parent | 02c997122f5f070c2196b86799fa77c85cc22383 (diff) | |
download | coreboot-3664647a25f31a26993433dcb6754484f58a9a62.tar.xz |
sb/intel/i82801gx: Add the option to lock the platform
This allows to lock down spi among other things
Mostly copied from bd82x6x.
Tested on Intel DG41WV with the MRC_CACHE driver write protecting the
mrc_cache region.
Change-Id: If9c3a6118f4586d51c093edec896c347ba904b8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx.h')
-rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1038bafdab..36c79eb5d1 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -368,6 +368,53 @@ int southbridge_detect_s3_resume(void); #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 +#define TCO1_CNT 0x68 + +/* SPIBAR + * + * SPI Opcode Menu setup for SPIBAR lockdown + * should support most common flash chips. + */ + +#define PREOP 0x54 +#define OPTYPE 0x56 +#define OPMENU 0x58 + +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ |