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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-10 23:13:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-06 10:38:22 +0000 |
| commit | 5eb81bed2ea503aaf910430da492ed75d27ef94f (patch) | |
| tree | 562c5611149b81c7b81d96c242feff2fe3dede78 /src/southbridge/intel/i82801gx/i82801gx.h | |
| parent | fefe7afeb0abb9d779f1e3b025dde6e1164dac9d (diff) | |
| download | coreboot-5eb81bed2ea503aaf910430da492ed75d27ef94f.tar.xz | |
sb/intel/i82801gx: Detect if the southbridge supports AHCI
This automatically detects whether the southbridge supports AHCI.
If AHCI support is selected it will be used unless "sata_no_ahci" is
set in the devicetree to override the behavior.
Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index e44fcf5123..76420b4e17 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -82,6 +82,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #define FDVCT 0xe4 #define PCIE_4_PORTS_MAX (1 << 7) +#define AHCI_UNSUPPORTED (1 << 3) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) |