diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-09 12:02:52 +0100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-03-22 17:55:53 +0100 |
commit | 3f111b0b11cf3d14b9aded601b6a1dd84f35a8dc (patch) | |
tree | a11b02549c808bd7a59ee762a73bd46561731ea3 /src/southbridge/intel/i82801gx/lpc.c | |
parent | 70a8e34853d4b01ab7a2089821c35715c59b4415 (diff) | |
download | coreboot-3f111b0b11cf3d14b9aded601b6a1dd84f35a8dc.tar.xz |
southbridge/intel/i82801gx: Fix problems found by checkpatch.pl
Change-Id: Iddc67e7c126ce19429afc24b021e385353564cb8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18705
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/lpc.c')
-rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 37 |
1 files changed, 20 insertions, 17 deletions
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a995e9fc45..e650d823aa 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -109,7 +109,7 @@ static void i82801gx_pirq_init(device_t dev) */ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -117,10 +117,14 @@ static void i82801gx_pirq_init(device_t dev) int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; + case 1: + /* INTA# */ int_line = config->pirqa_routing; break; + case 2: + /* INTB# */ int_line = config->pirqb_routing; break; + case 3: + /* INTC# */ int_line = config->pirqc_routing; break; + case 4: + /* INTD# */ int_line = config->pirqd_routing; break; } if (!int_line) @@ -168,7 +172,7 @@ static void i82801gx_power_options(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; int nmi_option; /* Which state do we want to goto after g3 (power restored)? @@ -221,7 +225,7 @@ static void i82801gx_power_options(device_t dev) reg8 &= ~(1 << 7); /* Set NMI. */ } else { printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); @@ -321,7 +325,7 @@ static void enable_clock_gating(void) reg32 |= (1 << 3) | (1 << 1); // DMI clock gating reg32 |= (1 << 2); // PCIe clock gating; reg32 &= ~(1 << 20); // No static clock gating for USB - reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating + reg32 &= ~((1 << 29) | (1 << 28)); // Disable UHCI clock gating RCBA32(CG) = reg32; } @@ -481,9 +485,9 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -void acpi_fill_fadt(acpi_fadt_t * fadt) +void acpi_fill_fadt(acpi_fadt_t *fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -586,19 +590,17 @@ void acpi_fill_fadt(acpi_fadt_t * fadt) fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) { + if (chip->p_cnt_throttling_supported) fadt->duty_width = 3; - } else { + else fadt->duty_width = 0; - } fadt->iapc_boot_arch = 0x03; fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER | ACPI_FADT_C2_MP_SUPPORTED); - if (chip->docking_supported) { + if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; - } } static void i82801gx_lpc_read_resources(device_t dev) @@ -643,7 +645,8 @@ static void i82801gx_lpc_read_resources(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(device_t dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -656,7 +659,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) static void southbridge_inject_dsdt(device_t dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |