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authorAngel Pons <th3fanbus@gmail.com>2020-06-08 12:32:54 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 21:33:35 +0000
commitd19332ca3a68eeadcae73d5660834bcaadf02030 (patch)
treea9d216831bbb150523db9bf803b4aa9afc7ad67f /src/southbridge/intel/i82801gx/pci.c
parent302a1437cd4393961cc8cca02fb56e64a9a73043 (diff)
downloadcoreboot-d19332ca3a68eeadcae73d5660834bcaadf02030.tar.xz
sb/intel/i82801gx: Use PCI bitwise ops
While we are at it, also reflow a few lines that fit in 96 characters. Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/i82801gx/pci.c')
-rw-r--r--src/southbridge/intel/i82801gx/pci.c20
1 files changed, 6 insertions, 14 deletions
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 74724383a2..d72bd81ebb 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -10,29 +10,21 @@
static void pci_init(struct device *dev)
{
u16 reg16;
- u8 reg8;
/* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* This device has no interrupt */
pci_write_config8(dev, INTR, 0xff);
- /* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
- reg16 &= ~PCI_BRIDGE_CTL_PARITY;
- reg16 &= ~PCI_BRIDGE_CTL_SERR;
- pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
+ /* Disable parity error response and SERR */
+ pci_and_config16(dev, PCI_BRIDGE_CONTROL,
+ ~(PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR));
/* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, SMLT);
- reg8 &= 0x07;
- reg8 |= (0x04 << 3);
- pci_write_config8(dev, SMLT, reg8);
+ pci_update_config8(dev, SMLT, 0x07, 0x04 << 3);
- /* Clear errors in status registers */
+ /* Clear errors in status registers. FIXME: Do something? */
reg16 = pci_read_config16(dev, PSTS);
//reg16 |= 0xf900;
pci_write_config16(dev, PSTS, reg16);