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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-21 18:36:06 +0200
committerMartin Roth <martinroth@google.com>2016-08-28 18:26:07 +0200
commit70d79a454676b551f3bc2059217179e31905ee5c (patch)
tree1a27cd7c57a9d46d0c7d6e7aaeb361c73dfac872 /src/southbridge/intel/i82801gx/sata.c
parent03b040b95f1a16d07b98e15c1aeef77ec7a4eca9 (diff)
downloadcoreboot-70d79a454676b551f3bc2059217179e31905ee5c.tar.xz
src/southbridge: Add required space before opening parenthesis '('
Change-Id: I43b9b86fd51dbdc50108026099c60238f3012cbe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16290 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
Diffstat (limited to 'src/southbridge/intel/i82801gx/sata.c')
-rw-r--r--src/southbridge/intel/i82801gx/sata.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 9cb6f39c16..2fcb83d9a7 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -118,7 +118,7 @@ static void sata_init(struct device *dev)
/* Restrict ports - 0 and 2 only available */
ports &= 0x5;
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
/* Allow both Legacy and Native mode */
pci_write_config8(dev, 0x09, 0x8f);