diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-12-29 06:26:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:21:34 +0000 |
| commit | 661ad4666ca0e78195f6901fce7b44a7e56e6331 (patch) | |
| tree | 57c25cee551ec747dcfdf0e38f995a091d5fcd79 /src/southbridge/intel/i82801gx/smihandler.c | |
| parent | 286a0572e75ade325238617d15c136f74c4f67a4 (diff) | |
| download | coreboot-661ad4666ca0e78195f6901fce7b44a7e56e6331.tar.xz | |
ACPI: Select ACPI_SOC_NVS only where suitable
Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.
Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.
Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Diffstat (limited to 'src/southbridge/intel/i82801gx/smihandler.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/smihandler.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 03480a7903..67a8cf8cf4 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> +#include <soc/nvs.h> #include <southbridge/intel/common/pmutil.h> #include "i82801gx.h" @@ -15,8 +16,6 @@ #define G_SMRANE (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#include "nvs.h" - /* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; |