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author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-11 09:39:43 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-17 07:00:37 +0000 |
commit | a4dd33cc8b52f686908590bb41b1c69a9b6c5db5 (patch) | |
tree | 95cf94c3ff438647096ff3300f0972b2f5b797e3 /src/southbridge/intel/i82801gx/usb_ehci.c | |
parent | a3022056a2d16b92cc0cdf5eafa4e6369c09e716 (diff) | |
download | coreboot-a4dd33cc8b52f686908590bb41b1c69a9b6c5db5.tar.xz |
src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers
Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44371
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx/usb_ehci.c')
-rw-r--r-- | src/southbridge/intel/i82801gx/usb_ehci.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 0a66136d03..b01af96c60 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -7,6 +7,7 @@ #include "i82801gx.h" #include <device/pci_ehci.h> #include <device/mmio.h> +#include <device/pci_def.h> #include <device/pci_ops.h> static void usb_ehci_init(struct device *dev) @@ -23,7 +24,7 @@ static void usb_ehci_init(struct device *dev) pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17)); /* Clear any pending port changes */ - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); base = res2mmio(res, 0, 0); reg32 = read32(base + 0x24) | (1 << 2); write32(base + 0x24, reg32); |