summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801gx
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-10-24 23:36:41 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-11-02 10:41:35 +0000
commit22d4397913ca3a3b42ad24b44f20ee08bee19b22 (patch)
tree83f763856146f82959ab976c0f53dad05226b1a0 /src/southbridge/intel/i82801gx
parent554713ee0a32cd8eabd75b276aeb82aa2570b030 (diff)
downloadcoreboot-22d4397913ca3a3b42ad24b44f20ee08bee19b22.tar.xz
azalia: Use `HDA_GCTL_CRST` macro as unset-mask
The `HDA_GCTL_CRST` corresponds to bit zero, so this is equivalent. Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46728 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
-rw-r--r--src/southbridge/intel/i82801gx/azalia.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index 6cf1fea165..1927adc749 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -43,11 +43,11 @@ static int codec_detect(u8 *base)
u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0)
+ if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
+ if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */