printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

14 files changed, 228 insertions, 228 deletions

diff --git a/src/southbridge/intel/i82801gx/i82801gx_ac97.c b/src/southbridge/intel/i82801gx/i82801gx_ac97.c
index f1e410715b..602014bb2e 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_ac97.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_ac97.c
@@ -101,7 +101,7 @@ static int ac97_semaphore(void)
 		timeout--;
 	} while ((reg8 & 1) && timeout);
 	if (! timeout) {
-		printk_debug("Timeout!\n");
+		printk(BIOS_DEBUG, "Timeout!\n");
 	}
 
 	return (!timeout);
@@ -123,7 +123,7 @@ static void ac97_audio_init(struct device *dev)
 	u32 reg32;
 	int i;
 
-	printk_debug("Initializing AC'97 Audio.\n");
+	printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");
 
 	/* top 16 bits are zero, so don't read them */
 	nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
@@ -142,7 +142,7 @@ static void ac97_audio_init(struct device *dev)
 	reg32 = inl(nabmbar + GLOB_STA);
 	if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
 		/* Primary Codec not found */
-		printk_debug("No primary codec. Disabling AC'97 Audio.\n");
+		printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");
 		return;
 	}
 
@@ -152,7 +152,7 @@ static void ac97_audio_init(struct device *dev)
 	outw(0x8000, nambar + MASTER_VOL);
 	ac97_semaphore();
 	if (inw(nambar + MASTER_VOL) != 0x8000) {
-		printk_debug("Codec not programmable. Disabling AC'97 Audio.\n");
+		printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");
 		return;
 	}
 
diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
index 60b7334c2c..a4cf14c4f9 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
@@ -86,7 +86,7 @@ no_codec:
 	/* Codec Not found */
 	/* Put HDA back in reset (BAR + 0x8) [0] */
 	set_bits(base + 0x08, 1, 0);
-	printk_debug("Azalia: No codec!\n");
+	printk(BIOS_DEBUG, "Azalia: No codec!\n");
 	return 0;
 }
 
@@ -170,7 +170,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
 	u32 verb_size;
 	int i;
 
-	printk_debug("Azalia: Initializing codec #%d\n", addr);
+	printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
 
 	/* 1 */
 	if (wait_for_ready(base) == -1)
@@ -185,14 +185,14 @@ static void codec_init(struct device *dev, u32 base, int addr)
 	reg32 = read32(base + 0x64);
 
 	/* 2 */
-	printk_debug("Azalia: codec viddid: %08x\n", reg32);
+	printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
 	verb_size = find_verb(dev, reg32, &verb);
 
 	if (!verb_size) {
-		printk_debug("Azalia: No verb!\n");
+		printk(BIOS_DEBUG, "Azalia: No verb!\n");
 		return;
 	}
-	printk_debug("Azalia: verb_size: %d\n", verb_size);
+	printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
 
 	/* 3 */
 	for (i = 0; i < verb_size; i++) {
@@ -204,7 +204,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
 		if (wait_for_valid(base) == -1)
 			return;
 	}
-	printk_debug("Azalia: verb loaded.\n");
+	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
 }
 
 static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
@@ -275,7 +275,7 @@ static void azalia_init(struct device *dev)
 	pci_write_config8(dev, 0x40, reg8);
 	mdelay(1);
 	reg8 = pci_read_config8(dev, 0x40);
-	printk_debug("Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
+	printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
 
 	//
 	reg8 = pci_read_config8(dev, 0x40); // Audio Control
@@ -304,11 +304,11 @@ static void azalia_init(struct device *dev)
 	// NOTE this will break as soon as the Azalia get's a bar above
 	// 4G. Is there anything we can do about it?
 	base = (u32)res->base;
-	printk_debug("Azalia: base = %08x\n", (u32)base);
+	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
-		printk_debug("Azalia: codec_mask = %02x\n", codec_mask);
+		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
 		codecs_init(dev, base, codec_mask);
 	}
 }
diff --git a/src/southbridge/intel/i82801gx/i82801gx_ide.c b/src/southbridge/intel/i82801gx/i82801gx_ide.c
index 28a1c055ea..84b50d6535 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_ide.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_ide.c
@@ -35,9 +35,9 @@ static void ide_init(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	printk_debug("i82801gx_ide: initializing... ");
+	printk(BIOS_DEBUG, "i82801gx_ide: initializing... ");
 	if (config == NULL) {
-		printk_err("\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
+		printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
 		// Trying to set somewhat safe defaults instead of bailing out.
 		enable_primary = enable_secondary = 1;
 	} else {
@@ -61,7 +61,7 @@ static void ide_init(struct device *dev)
 		ideTimingConfig |= (3 << 8); // RCT = 1 clock
 		ideTimingConfig |= (1 << 1); // IE0
 		ideTimingConfig |= (1 << 0); // TIME0
-		printk_debug("IDE0 ");
+		printk(BIOS_DEBUG, "IDE0 ");
 	}
 	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
@@ -75,7 +75,7 @@ static void ide_init(struct device *dev)
 		ideTimingConfig |= (3 << 8); // RCT = 1 clock
 		ideTimingConfig |= (1 << 1); // IE0
 		ideTimingConfig |= (1 << 0); // TIME0
-		printk_debug("IDE1 ");
+		printk(BIOS_DEBUG, "IDE1 ");
 	}
 	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 
@@ -92,7 +92,7 @@ static void ide_init(struct device *dev)
 	/* Interrupt Pin is set by D31IP.PIP */
 	pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */
 
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
index ccab5482c9..f0e48ec29e 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
@@ -52,16 +52,16 @@ static void i82801gx_enable_apic(struct device *dev)
 
 	*ioapic_index = 0;
 	reg32 = *ioapic_data;
-	printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
 	if (reg32 != (1 << 25))
 		die("APIC Error\n");
 
-	printk_spew("Dumping IOAPIC registers\n");
+	printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
 	for (i=0; i<3; i++) {
 		*ioapic_index = i;
-		printk_spew("  reg 0x%04x:", i);
+		printk(BIOS_SPEW, "  reg 0x%04x:", i);
 		reg32 = *ioapic_data;
-		printk_spew(" 0x%08x\n", reg32);
+		printk(BIOS_SPEW, " 0x%08x\n", reg32);
 	}
 
 	*ioapic_index = 3; /* Select Boot Configuration register. */
@@ -213,7 +213,7 @@ static void i82801gx_power_options(device_t dev)
 	reg8 &= ~(1 << 3);	/* minimum asssertion is 1 to 2 RTCCLK */
 
 	pci_write_config8(dev, GEN_PMCON_3, reg8);
-	printk_info("Set power %s after power failure.\n", state);
+	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 
 	/* Set up NMI on errors. */
 	reg8 = inb(0x61);
@@ -227,10 +227,10 @@ static void i82801gx_power_options(device_t dev)
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
 	if (nmi_option) {
-		printk_info ("NMI sources enabled.\n");
+		printk(BIOS_INFO, "NMI sources enabled.\n");
 		reg8 &= ~(1 << 7);	/* Set NMI. */
 	} else {
-		printk_info ("NMI sources disabled.\n");
+		printk(BIOS_INFO, "NMI sources disabled.\n");
 		reg8 |= ( 1 << 7);	/* Can't mask NMI from PCI-E and NMI_NOW */
 	}
 	outb(reg8, 0x70);
@@ -296,7 +296,7 @@ static void i82801gx_rtc_init(struct device *dev)
 		reg8 &= ~RTC_BATTERY_DEAD;
 		pci_write_config8(dev, GEN_PMCON_3, reg8);
 	}
-	printk_debug("rtc_failed = 0x%x\n", rtc_failed);
+	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 
 	rtc_init(rtc_failed);
 }
@@ -340,13 +340,13 @@ static void i82801gx_lock_smm(struct device *dev)
 #endif
 
 #if ENABLE_ACPI_MODE_IN_COREBOOT
-	printk_debug("Enabling ACPI via APMC:\n");
+	printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
 	outb(0xe1, 0xb2); // Enable ACPI mode
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #else
-	printk_debug("Disabling ACPI via APMC:\n");
+	printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
 	outb(0x1e, 0xb2); // Disable ACPI mode
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 	/* Don't allow evil boot loaders, kernels, or
 	 * userspace applications to deceive us:
@@ -355,29 +355,29 @@ static void i82801gx_lock_smm(struct device *dev)
 
 #if TEST_SMM_FLASH_LOCKDOWN
 	/* Now try this: */
-	printk_debug("Locking BIOS to RO... ");
+	printk(BIOS_DEBUG, "Locking BIOS to RO... ");
 	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
-	printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 			(reg8&1)?"rw":"ro");
 	reg8 &= ~(1 << 0);			/* clear BIOSWE */
 	pci_write_config8(dev, 0xdc, reg8);
 	reg8 |= (1 << 1);			/* set BLE */
 	pci_write_config8(dev, 0xdc, reg8);
-	printk_debug("ok.\n");
+	printk(BIOS_DEBUG, "ok.\n");
 	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
-	printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 			(reg8&1)?"rw":"ro");
 
-	printk_debug("Writing:\n");
+	printk(BIOS_DEBUG, "Writing:\n");
 	*(volatile u8 *)0xfff00000 = 0x00;
-	printk_debug("Testing:\n");
+	printk(BIOS_DEBUG, "Testing:\n");
 	reg8 |= (1 << 0);			/* set BIOSWE */
 	pci_write_config8(dev, 0xdc, reg8);
 
 	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
-	printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 			(reg8&1)?"rw":"ro");
-	printk_debug("Done.\n");
+	printk(BIOS_DEBUG, "Done.\n");
 #endif
 }
 #endif
@@ -406,7 +406,7 @@ static void i82801gx_fixups(struct device *dev)
 
 static void lpc_init(struct device *dev)
 {
-	printk_debug("i82801gx: lpc_init\n");
+	printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
 
 	/* Set the value for PCI command register. */
 	pci_write_config16(dev, PCI_COMMAND, 0x000f);
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c
index d9057cb295..c4c22f0ae8 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pci.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c
@@ -71,7 +71,7 @@ static void ich_pci_dev_enable_resources(struct device *dev)
 	/* Set the subsystem vendor and device id for mainboard devices */
 	ops = ops_pci(dev);
 	if (dev->on_mainboard && ops && ops->set_subsystem) {
-		printk_debug("%s subsystem <- %02x/%02x\n",
+		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
 			dev_path(dev),
 			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
 			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
@@ -87,10 +87,10 @@ static void ich_pci_dev_enable_resources(struct device *dev)
 	 * this will cause the ROM and APICs not being visible
 	 * anymore.
 	 */
-	printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
+	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
 	pci_write_config16(dev, PCI_COMMAND, command);
 #else
-	printk_debug("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+	printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
 #endif
 }
 
@@ -105,7 +105,7 @@ static void ich_pci_bus_enable_resources(struct device *dev)
 	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 	ctrl |= dev->link[0].bridge_ctrl;
 	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
-	printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+	printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 
 	/* This is the reason we need our own pci_bus_enable_resources */
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
index b66a887063..d69bc6d07d 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
@@ -28,7 +28,7 @@ static void pci_init(struct device *dev)
 	u16 reg16;
 	u32 reg32;
 
-	printk_debug("Initializing ICH7 PCIe bridge.\n");
+	printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
 
 	/* Enable Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -77,13 +77,13 @@ static void pci_init(struct device *dev)
 
 #ifdef EVEN_MORE_DEBUG
 	reg32 = pci_read_config32(dev, 0x20);
-	printk_spew("    MBL    = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "    MBL    = 0x%08x\n", reg32);
 	reg32 = pci_read_config32(dev, 0x24);
-	printk_spew("    PMBL   = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "    PMBL   = 0x%08x\n", reg32);
 	reg32 = pci_read_config32(dev, 0x28);
-	printk_spew("    PMBU32 = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "    PMBU32 = 0x%08x\n", reg32);
 	reg32 = pci_read_config32(dev, 0x2c);
-	printk_spew("    PMLU32 = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "    PMLU32 = 0x%08x\n", reg32);
 #endif
 
 	/* Clear errors in status registers */
diff --git a/src/southbridge/intel/i82801gx/i82801gx_sata.c b/src/southbridge/intel/i82801gx/i82801gx_sata.c
index ec477e1696..50cdb48131 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_sata.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_sata.c
@@ -33,10 +33,10 @@ static void sata_init(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	printk_debug("i82801gx_sata: initializing...\n");
+	printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
 
 	if (config == NULL) {
-		printk_err("i82801gx_sata: error: device not in Config.lb!\n");
+		printk(BIOS_ERR, "i82801gx_sata: error: device not in Config.lb!\n");
 		return;
 	}
 
@@ -46,7 +46,7 @@ static void sata_init(struct device *dev)
 	pci_write_config16(dev, PCI_COMMAND, 0x0007);
 
 	if (config->ide_legacy_combined) {
-		printk_debug("SATA controller in combined mode.\n");
+		printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
 		/* No AHCI: clear AHCI base */
 		pci_write_config32(dev, 0x24, 0x00000000);
 		/* And without AHCI BAR no memory decoding */
@@ -80,7 +80,7 @@ static void sata_init(struct device *dev)
 		/* SATA Initialization register */
 		pci_write_config32(dev, 0x94, 0x5a000180);
 	} else if(config->sata_ahci) {
-		printk_debug("SATA controller in AHCI mode.\n");
+		printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
 		/* Allow both Legacy and Native mode */
 		pci_write_config8(dev, 0x09, 0x8f);
 
@@ -112,7 +112,7 @@ static void sata_init(struct device *dev)
 		/* SATA Initialization register */
 		pci_write_config32(dev, 0x94, 0x1a000180);
 	} else {
-		printk_debug("SATA controller in plain mode.\n");
+		printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
 		/* Set Sata Controller Mode. No Mapping(?) */
 		pci_write_config8(dev, 0x90, 0x00);
 
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smbus.c b/src/southbridge/intel/i82801gx/i82801gx_smbus.c
index 4306055d37..50c6d0f342 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smbus.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_smbus.c
@@ -35,11 +35,11 @@ static void smbus_init(struct device *dev)
 	u32 smb_base;
 
 	smb_base = pci_read_config32(dev, SMB_BASE);
-	printk_debug("Initializing SMBus device:\n");
-	printk_debug("  Old SMBUS Base Address: 0x%04x\n", smb_base);
+	printk(BIOS_DEBUG, "Initializing SMBus device:\n");
+	printk(BIOS_DEBUG, "  Old SMBUS Base Address: 0x%04x\n", smb_base);
 	pci_write_config32(dev, SMB_BASE, 0x00000401);
 	smb_base = pci_read_config32(dev, SMB_BASE);
-	printk_debug("  New SMBUS Base Address: 0x%04x\n", smb_base);
+	printk(BIOS_DEBUG, "  New SMBUS Base Address: 0x%04x\n", smb_base);
 }
 
 static int lsmbus_read_byte(device_t dev, u8 address)
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smi.c b/src/southbridge/intel/i82801gx/i82801gx_smi.c
index 0c70812412..3ba21b0dd1 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smi.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_smi.c
@@ -63,16 +63,16 @@ static u16 reset_pm1_status(void)
 
 static void dump_pm1_status(u16 pm1_sts)
 {
-	printk_debug("PM1_STS: ");
-	if (pm1_sts & (1 << 15)) printk_debug("WAK ");
-	if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
-	if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
-	if (pm1_sts & (1 << 10)) printk_debug("RTC ");
-	if (pm1_sts & (1 <<  8)) printk_debug("PWRBTN ");
-	if (pm1_sts & (1 <<  5)) printk_debug("GBL ");
-	if (pm1_sts & (1 <<  4)) printk_debug("BM ");
-	if (pm1_sts & (1 <<  0)) printk_debug("TMROF ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_DEBUG, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_DEBUG, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_DEBUG, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_DEBUG, "TMROF ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 /**
@@ -92,28 +92,28 @@ static u32 reset_smi_status(void)
 
 static void dump_smi_status(u32 smi_sts)
 {
-	printk_debug("SMI_STS: ");
-	if (smi_sts & (1 << 26)) printk_debug("SPI ");
-	if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
-	if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
-	if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
-	if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
-	if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
-	if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
-	if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
-	if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
-	if (smi_sts & (1 << 13)) printk_debug("TCO ");
-	if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
-	if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
-	if (smi_sts & (1 << 10)) printk_debug("GPI ");
-	if (smi_sts & (1 <<  9)) printk_debug("GPE0 ");
-	if (smi_sts & (1 <<  8)) printk_debug("PM1 ");
-	if (smi_sts & (1 <<  6)) printk_debug("SWSMI_TMR ");
-	if (smi_sts & (1 <<  5)) printk_debug("APM ");
-	if (smi_sts & (1 <<  4)) printk_debug("SLP_SMI ");
-	if (smi_sts & (1 <<  3)) printk_debug("LEGACY_USB ");
-	if (smi_sts & (1 <<  2)) printk_debug("BIOS ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -135,25 +135,25 @@ static u32 reset_gpe0_status(void)
 static void dump_gpe0_status(u32 gpe0_sts)
 {
 	int i;
-	printk_debug("GPE0_STS: ");
+	printk(BIOS_DEBUG, "GPE0_STS: ");
 	for (i=31; i<= 16; i--) {
-		if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
 	}
-	if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
-	if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
-	if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
-	if (gpe0_sts & (1 << 11)) printk_debug("PME ");
-	if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
-	if (gpe0_sts & (1 <<  9)) printk_debug("PCI_EXP ");
-	if (gpe0_sts & (1 <<  8)) printk_debug("RI ");
-	if (gpe0_sts & (1 <<  7)) printk_debug("SMB_WAK ");
-	if (gpe0_sts & (1 <<  6)) printk_debug("TCO_SCI ");
-	if (gpe0_sts & (1 <<  5)) printk_debug("AC97 ");
-	if (gpe0_sts & (1 <<  4)) printk_debug("USB2 ");
-	if (gpe0_sts & (1 <<  3)) printk_debug("USB1 ");
-	if (gpe0_sts & (1 <<  2)) printk_debug("HOT_PLUG ");
-	if (gpe0_sts & (1 <<  0)) printk_debug("THRM ");
-	printk_debug("\n");
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -175,11 +175,11 @@ static u16 reset_alt_gp_smi_status(void)
 static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
 {
 	int i;
-	printk_debug("ALT_GP_SMI_STS: ");
+	printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
 	for (i=15; i<= 0; i--) {
-		if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16));
+		if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16));
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -205,21 +205,21 @@ static u32 reset_tco_status(void)
 
 static void dump_tco_status(u32 tco_sts)
 {
-	printk_debug("TCO_STS: ");
-	if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
-	if (tco_sts & (1 << 18)) printk_debug("BOOT ");
-	if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
-	if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
-	if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
-	if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
-	if (tco_sts & (1 <<  9)) printk_debug("DMISCI ");
-	if (tco_sts & (1 <<  8)) printk_debug("BIOSWR ");
-	if (tco_sts & (1 <<  7)) printk_debug("NEWCENTURY ");
-	if (tco_sts & (1 <<  3)) printk_debug("TIMEOUT ");
-	if (tco_sts & (1 <<  2)) printk_debug("TCO_INT ");
-	if (tco_sts & (1 <<  1)) printk_debug("SW_TCO ");
-	if (tco_sts & (1 <<  0)) printk_debug("NMI2SMI ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -243,14 +243,14 @@ static void smm_relocate(void)
 	u32 smi_en;
 	u16 pm1_en;
 
-	printk_debug("Initializing SMM handler...");
+	printk(BIOS_DEBUG, "Initializing SMM handler...");
 
 	pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;
-	printk_spew(" ... pmbase = 0x%04x\n", pmbase);
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
 
 	smi_en = inl(pmbase + SMI_EN);
 	if (smi_en & APMC_EN) {
-		printk_info("SMI# handler already enabled?\n");
+		printk(BIOS_INFO, "SMI# handler already enabled?\n");
 		return;
 	}
 
@@ -258,7 +258,7 @@ static void smm_relocate(void)
 	memcpy((void *)0x38000, &smm_relocation_start,
 			&smm_relocation_end - &smm_relocation_start);
 
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 	dump_smi_status(reset_smi_status());
 	dump_pm1_status(reset_pm1_status());
 	dump_gpe0_status(reset_gpe0_status());
@@ -314,7 +314,7 @@ static void smm_relocate(void)
 	 */
 
 	/* raise an SMI interrupt */
-	printk_spew("  ... raise SMI#\n");
+	printk(BIOS_SPEW, "  ... raise SMI#\n");
 	outb(0x00, 0xb2);
 }
 
@@ -349,7 +349,7 @@ void smm_lock(void)
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */
-	printk_debug("Locking SMM.\n");
+	printk(BIOS_DEBUG, "Locking SMM.\n");
 	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
 			D_LCK | G_SMRAME | C_BASE_SEG);
 }
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
index 9cd0370cdc..b478dbaa90 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
@@ -76,18 +76,18 @@ static u16 reset_pm1_status(void)
 
 static void dump_pm1_status(u16 pm1_sts)
 {
-	printk_spew("PM1_STS: ");
-	if (pm1_sts & (1 << 15)) printk_spew("WAK ");
-	if (pm1_sts & (1 << 14)) printk_spew("PCIEXPWAK ");
-	if (pm1_sts & (1 << 11)) printk_spew("PRBTNOR ");
-	if (pm1_sts & (1 << 10)) printk_spew("RTC ");
-	if (pm1_sts & (1 <<  8)) printk_spew("PWRBTN ");
-	if (pm1_sts & (1 <<  5)) printk_spew("GBL ");
-	if (pm1_sts & (1 <<  4)) printk_spew("BM ");
-	if (pm1_sts & (1 <<  0)) printk_spew("TMROF ");
-	printk_spew("\n");
+	printk(BIOS_SPEW, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_SPEW, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_SPEW, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_SPEW, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_SPEW, "TMROF ");
+	printk(BIOS_SPEW, "\n");
 	int reg16 = inw(pmbase + PM1_EN);
-	printk_spew("PM1_EN: %x\n", reg16);
+	printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
 }
 
 /**
@@ -107,28 +107,28 @@ static u32 reset_smi_status(void)
 
 static void dump_smi_status(u32 smi_sts)
 {
-	printk_debug("SMI_STS: ");
-	if (smi_sts & (1 << 26)) printk_debug("SPI ");
-	if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
-	if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
-	if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
-	if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
-	if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
-	if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
-	if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
-	if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
-	if (smi_sts & (1 << 13)) printk_debug("TCO ");
-	if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
-	if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
-	if (smi_sts & (1 << 10)) printk_debug("GPI ");
-	if (smi_sts & (1 <<  9)) printk_debug("GPE0 ");
-	if (smi_sts & (1 <<  8)) printk_debug("PM1 ");
-	if (smi_sts & (1 <<  6)) printk_debug("SWSMI_TMR ");
-	if (smi_sts & (1 <<  5)) printk_debug("APM ");
-	if (smi_sts & (1 <<  4)) printk_debug("SLP_SMI ");
-	if (smi_sts & (1 <<  3)) printk_debug("LEGACY_USB ");
-	if (smi_sts & (1 <<  2)) printk_debug("BIOS ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -150,25 +150,25 @@ static u32 reset_gpe0_status(void)
 static void dump_gpe0_status(u32 gpe0_sts)
 {
 	int i;
-	printk_debug("GPE0_STS: ");
+	printk(BIOS_DEBUG, "GPE0_STS: ");
 	for (i=31; i<= 16; i--) {
-		if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
 	}
-	if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
-	if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
-	if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
-	if (gpe0_sts & (1 << 11)) printk_debug("PME ");
-	if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
-	if (gpe0_sts & (1 <<  9)) printk_debug("PCI_EXP ");
-	if (gpe0_sts & (1 <<  8)) printk_debug("RI ");
-	if (gpe0_sts & (1 <<  7)) printk_debug("SMB_WAK ");
-	if (gpe0_sts & (1 <<  6)) printk_debug("TCO_SCI ");
-	if (gpe0_sts & (1 <<  5)) printk_debug("AC97 ");
-	if (gpe0_sts & (1 <<  4)) printk_debug("USB2 ");
-	if (gpe0_sts & (1 <<  3)) printk_debug("USB1 ");
-	if (gpe0_sts & (1 <<  2)) printk_debug("HOT_PLUG ");
-	if (gpe0_sts & (1 <<  0)) printk_debug("THRM ");
-	printk_debug("\n");
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 
@@ -193,21 +193,21 @@ static u32 reset_tco_status(void)
 
 static void dump_tco_status(u32 tco_sts)
 {
-	printk_debug("TCO_STS: ");
-	if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
-	if (tco_sts & (1 << 18)) printk_debug("BOOT ");
-	if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
-	if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
-	if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
-	if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
-	if (tco_sts & (1 <<  9)) printk_debug("DMISCI ");
-	if (tco_sts & (1 <<  8)) printk_debug("BIOSWR ");
-	if (tco_sts & (1 <<  7)) printk_debug("NEWCENTURY ");
-	if (tco_sts & (1 <<  3)) printk_debug("TIMEOUT ");
-	if (tco_sts & (1 <<  2)) printk_debug("TCO_INT ");
-	if (tco_sts & (1 <<  1)) printk_debug("SW_TCO ");
-	if (tco_sts & (1 <<  0)) printk_debug("NMI2SMI ");
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
 }
 
 /* We are using PCIe accesses for now
@@ -220,7 +220,7 @@ int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
 	case 0x32:
-		printk_debug("OS Init\n");
+		printk(BIOS_DEBUG, "OS Init\n");
 		/* gnvs->smif:
 		 *  On success, the IO Trap Handler returns 0
 		 *  On failure, the IO Trap Handler returns a value != 0
@@ -299,23 +299,23 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 
 	/* Figure out SLP_TYP */
 	reg32 = inl(pmbase + PM1_CNT);
-	printk_spew("SMI#: SLP = 0x%08x\n", reg32);
+	printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
 	slp_typ = (reg32 >> 10) & 7;
 
 	/* Next, do the deed.
 	 */
 
 	switch (slp_typ) {
-	case 0: printk_debug("SMI#: Entering S0 (On)\n"); break;
-	case 1: printk_debug("SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+	case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+	case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
 	case 5:
-		printk_debug("SMI#: Entering S3 (Suspend-To-RAM)\n");
+		printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
 		/* Invalidate the cache before going to S3 */
 		wbinvd();
 		break;
-	case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+	case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
 	case 7:
-		printk_debug("SMI#: Entering S5 (Soft Power off)\n");
+		printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
 
 		outl(0, pmbase + GPE0_EN);
 
@@ -333,7 +333,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 		/* also iterates over all bridges on bus 0 */
 		busmaster_disable_on_bus(0);
 		break;
-	default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break;
+	default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
 	}
 
 	/* Write back to the SLP register to cause the originally intended
@@ -368,40 +368,40 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
-		printk_debug("C-state control\n");
+		printk(BIOS_DEBUG, "C-state control\n");
 		break;
 	case PST_CONTROL:
 		/* Calling this function seems to cause
 		 * some kind of race condition in Linux
 		 * and causes a kernel oops
 		 */
-		printk_debug("P-state control\n");
+		printk(BIOS_DEBUG, "P-state control\n");
 		break;
 	case ACPI_DISABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl &= ~SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
-		printk_debug("SMI#: ACPI disabled.\n");
+		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 		break;
 	case ACPI_ENABLE:
 		pmctrl = inl(pmbase + PM1_CNT);
 		pmctrl |= SCI_EN;
 		outl(pmctrl, pmbase + PM1_CNT);
-		printk_debug("SMI#: ACPI enabled.\n");
+		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
 	case GNVS_UPDATE:
 		if (smm_initialized) {
-			printk_debug("SMI#: SMM structures already initialized!\n");
+			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
 		}
 		gnvs = *(global_nvs_t **)0x500;
 		tcg  = *(void **)0x504;
 		smi1 = *(void **)0x508;
 		smm_initialized = 1;
-		printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
+		printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
 		break;
 	default:
-		printk_debug("SMI#: Unknown function APM_CNT=%02x\n", reg8);
+		printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
 	}
 }
 
@@ -445,7 +445,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
 		mainboard_smi_gpi(reg16);
 	} else {
 		if (reg16)
-			printk_debug("GPI (mask %04x)\n",reg16);
+			printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
 	}
 }
 
@@ -459,7 +459,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s
 	if ((reg32 & MCSMI_EN) == 0)
 		return;
 
-	printk_debug("Microcontroller SMI.\n");
+	printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }
 
 
@@ -490,12 +490,12 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
 			 * resolute answer would be to power down the
 			 * box.
 			 */
-			printk_debug("Switching back to RO\n");
+			printk(BIOS_DEBUG, "Switching back to RO\n");
 			pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
 		} /* No else for now? */
 	} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
 		/* Handle TCO timeout */
-		printk_debug("TCO Timeout.\n");
+		printk(BIOS_DEBUG, "TCO Timeout.\n");
 	} else if (!tco_sts) {
 		dump_tco_status(tco_sts);
 	}
@@ -511,7 +511,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s
 	if ((reg32 & PERIODIC_EN) == 0)
 		return;
 
-	printk_debug("Periodic SMI.\n");
+	printk(BIOS_DEBUG, "Periodic SMI.\n");
 }
 
 static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
@@ -544,7 +544,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
 	/* IOTRAP(0) SMIC */
 	if (IOTRAP(0)) {
 		if (!(trap_cycle & (1 << 24))) { // It's a write
-			printk_debug("SMI1 command\n");
+			printk(BIOS_DEBUG, "SMI1 command\n");
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
@@ -554,16 +554,16 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
 		// Fall through to debug
 	}
 
-	printk_debug("  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
-	for (i=0; i < 4; i++) if(IOTRAP(i)) printk_debug("  TRAP = %d\n", i);
-	printk_debug("  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
-	printk_debug("  MASK = 0x%08x\n", mask);
-	printk_debug("  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
+	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
+	for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
+	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
+	printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
 
 	if (!(trap_cycle & (1 << 24))) {
 		/* Write Cycle */
 		data = RCBA32(0x1e18);
-		printk_debug("  iotrap written data = 0x%08x\n", data);
+		printk(BIOS_DEBUG, "  iotrap written data = 0x%08x\n", data);
 	}
 #undef IOTRAP
 }
@@ -635,7 +635,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 			if (southbridge_smi[i])
 				southbridge_smi[i](node, state_save);
 			else {
-				printk_debug("SMI_STS[%d] occured, but no "
+				printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
 						"handler available.\n", i);
 				dump = 1;
 			}
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb.c b/src/southbridge/intel/i82801gx/i82801gx_usb.c
index 2803f9cdef..00fddf7c65 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb.c
@@ -30,7 +30,7 @@ static void usb_init(struct device *dev)
 	u8 reg8;
 
 	/* USB Specification says the device must be Bus Master */
-	printk_debug("UHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
 
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
@@ -43,7 +43,7 @@ static void usb_init(struct device *dev)
 	reg8 |= (1 << 0);
 	pci_write_config8(dev, 0xca, reg8);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
index 829ae6b819..ead7bdca7f 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
@@ -30,7 +30,7 @@ void set_debug_port(unsigned port)
 {
 	u32 dbgctl;
 
-	printk_debug("Enabling OWNER_CNT\n");
+	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
 	dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
 	dbgctl |= (1 << 30);
 	write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c b/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
index 3d61cae9b6..1bc5fcaecb 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
@@ -35,7 +35,7 @@ static void usb_ehci_init(struct device *dev)
 	u32 reg32;
 	u8 reg8;
 
-	printk_debug("EHCI: Setting up controller.. ");
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	reg32 |= PCI_COMMAND_MASTER;
 	reg32 |= PCI_COMMAND_SERR;
@@ -61,7 +61,7 @@ static void usb_ehci_init(struct device *dev)
 	reg8 |= (1 << 4);
 	pci_write_config8(dev, 0x84, reg8);
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
index 38350d7ef2..436a9227cd 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
@@ -49,5 +49,5 @@ void watchdog_off(void)
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
 
-	printk_debug("ICH7 watchdog disabled\r\n");
+	printk(BIOS_DEBUG, "ICH7 watchdog disabled\r\n");
 }