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authorElyes HAOUAS <ehaouas@noos.fr>2018-12-01 12:19:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-13 09:30:54 +0000
commit0c22d2fe46fbc59fa12fec46c21874f422b10e44 (patch)
tree56d001f97110805286469be248de0790d3eed7d4 /src/southbridge/intel/i82801gx
parent9005071c5fb1d75b2a54aa0b3e7af47e25d2de54 (diff)
downloadcoreboot-0c22d2fe46fbc59fa12fec46c21874f422b10e44.tar.xz
{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro
Use BIOS_CNTL defined macro instead of magic number. Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c32
1 files changed, 0 insertions, 32 deletions
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 9a6c9cfefd..948b6aa7f7 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -40,7 +40,6 @@
#define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
-#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_i82801gx_config config_t;
@@ -333,10 +332,6 @@ static void enable_clock_gating(void)
#if CONFIG(HAVE_SMI_HANDLER)
static void i82801gx_lock_smm(struct device *dev)
{
-#if TEST_SMM_FLASH_LOCKDOWN
- u8 reg8;
-#endif
-
if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
@@ -351,33 +346,6 @@ static void i82801gx_lock_smm(struct device *dev)
printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT);
}
-
-#if TEST_SMM_FLASH_LOCKDOWN
- /* Now try this: */
- printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
- reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
- reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
- printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
-
- printk(BIOS_DEBUG, "Writing:\n");
- *(volatile u8 *)0xfff00000 = 0x00;
- printk(BIOS_DEBUG, "Testing:\n");
- reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
-
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
- printk(BIOS_DEBUG, "Done.\n");
-#endif
}
#endif