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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-11-29 14:13:43 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-06 18:14:00 +0100 |
| commit | 62902ca45de871aa59657dd8ec1858c301595634 (patch) | |
| tree | 43b21ab2ec87ec5b41f875efb69be8bb494b0fa7 /src/southbridge/intel/i82801gx | |
| parent | 40843efe5d6dddff19a0d7c8c5fe84c75448e739 (diff) | |
| download | coreboot-62902ca45de871aa59657dd8ec1858c301595634.tar.xz | |
sb/ich7: Use common/gpio.h to set up GPIOs
This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 1f22d05526..b2265c4902 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select COMMON_FADT + select SOUTHBRIDGE_INTEL_COMMON_GPIO if SOUTHBRIDGE_INTEL_I82801GX |