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| author | Xiang Wang <wxjstz@126.com> | 2018-07-20 16:16:46 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-01 14:37:06 +0000 |
| commit | 07bc3251a9c74ecb4f96878b99e3537307c6c685 (patch) | |
| tree | 4079f16b3e9c73241a892b831634853e9a57d709 /src/southbridge/intel/i82801gx | |
| parent | ee09878f4520e04547757d5af9e597d44f9c82db (diff) | |
| download | coreboot-07bc3251a9c74ecb4f96878b99e3537307c6c685.tar.xz | |
riscv: remove redundancy in Makefile
src/arch/riscv/stages.c is an entry of romstage/ramstage, and does not
needs to be bootblock.
src/arch/riscv/id.S src/arch/riscv/id.ld is used to generate some
compile/board/time information, which is repeated with src/lib/version.c
Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27557
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
0 files changed, 0 insertions, 0 deletions