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authorElyes HAOUAS <ehaouas@noos.fr>2020-02-24 13:26:04 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-02-26 17:06:40 +0000
commit44f558ec262c671d4db76ae25eb1b8e24204d002 (patch)
treef66b2fe59486b6bcdb094822f9b57b4d09537b90 /src/southbridge/intel/i82801gx
parentdfd3f211740be4cf0d234bf4621ac384758a24ce (diff)
downloadcoreboot-44f558ec262c671d4db76ae25eb1b8e24204d002.tar.xz
treewide: capitalize 'USB'
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
-rw-r--r--src/southbridge/intel/i82801gx/early_init.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index a627cc15c7..fa578f7cec 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -99,7 +99,7 @@ void i82801gx_early_init(void)
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
- /* usb transient disconnect */
+ /* USB transient disconnect */
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
reg8 |= (3 << 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);