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authorPatrick Georgi <patrick.georgi@secunet.com>2011-11-22 10:52:43 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-24 20:40:42 +0100
commit8a85bccd8404c705891ae9f3851952ff8bfa1f76 (patch)
tree1785e6e79daa90fad85dca3bc8adbc2d27a0b184 /src/southbridge/intel/i82801gx
parentc07466b287b0aaba0fc73decc60bb75fe919fea1 (diff)
downloadcoreboot-8a85bccd8404c705891ae9f3851952ff8bfa1f76.tar.xz
i82801gx: Support power-on-after-power-fail better
Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/444 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
-rw-r--r--src/southbridge/intel/i82801gx/smihandler.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 5cc25e7ae2..401c9adcf8 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -316,16 +316,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
outl(0, pmbase + GPE0_EN);
- /* Should we keep the power state after a power loss?
- * In case the setting is "ON" or "OFF" we don't have
- * to do anything. But if it's "KEEP" we have to switch
- * to "OFF" before entering S5.
+ /* Always set the flag in case CMOS was changed on runtime. For
+ * "KEEP", switch to "OFF" - KEEP is software emulated
*/
- if (s5pwr == MAINBOARD_POWER_KEEP) {
- reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ if (s5pwr == MAINBOARD_POWER_ON) {
+ reg8 &= ~1;
+ } else {
reg8 |= 1;
- pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
}
+ pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);