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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-08-15 20:59:09 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-14 21:43:25 +0000 |
| commit | b451df2f400ba12fff440247330f8b57a93034bd (patch) | |
| tree | 8bb52821a42aaaea2e614910d97b1ae4e690b7c2 /src/southbridge/intel/i82801gx | |
| parent | e4a016ff17b455a8acd0ea72b30caabb622ce224 (diff) | |
| download | coreboot-b451df2f400ba12fff440247330f8b57a93034bd.tar.xz | |
mb/*/*/romstage.c: Clean up targets with i82801gx
Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index b3c1b48ec2..df744fc73c 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -125,6 +125,11 @@ int southbridge_detect_s3_resume(void); #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ +#define GEN1_DEC 0x84 +#define GEN2_DEC 0x88 +#define GEN3_DEC 0x8c +#define GEN4_DEC 0x90 + /* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |