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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 10:25:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:23:06 +0000 |
| commit | b9d2e228b63c898383f1f6e6bd5e02b018ff31af (patch) | |
| tree | 97c6a7a793e568e3b7f65b85373c86db7ceef1b6 /src/southbridge/intel/i82801ix/pcie.c | |
| parent | 73ae076e954ea6acd2fd22386616cd4ce839c830 (diff) | |
| download | coreboot-b9d2e228b63c898383f1f6e6bd5e02b018ff31af.tar.xz | |
sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I5a07a00e1183ef834d97c11268935617cfe17faa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801ix/pcie.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/pcie.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index d170f0de44..5471e6979f 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -20,9 +20,7 @@ static void pci_init(struct device *dev) printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it |