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authorKevin Paul Herbert <kph@meraki.net>2014-12-24 18:43:20 -0800
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-15 08:50:22 +0100
commitbde6d309dfafe58732ec46314a2d4c08974b62d4 (patch)
tree17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/intel/i82801ix/sata.c
parent4b10dec1a66122b515b2191f823d7fd379ec655f (diff)
downloadcoreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.tar.xz
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/i82801ix/sata.c')
-rw-r--r--src/southbridge/intel/i82801ix/sata.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index 10c8a2bd15..f65eba26b4 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -36,8 +36,8 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
u32 reg32;
/* Initialize AHCI memory-mapped space */
- const u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Set AHCI access mode.
No other ABAR registers should be accessed before this. */
@@ -67,7 +67,7 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
for (i = 0; i < 6; ++i) {
if (((i == 2) || (i == 3)) && is_mobile)
continue;
- const u32 addr = abar + 0x118 + (i * 0x80);
+ u8 *addr = abar + 0x118 + (i * 0x80);
write32(addr, read32(addr));
}
}