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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-26 08:35:09 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-10 18:20:34 +0200 |
| commit | 9b143e1474f425b6d81bf6490d67baf26d03c437 (patch) | |
| tree | a741e62aab6d51d33ddc74046233948f8841c441 /src/southbridge/intel/i82801ix/smihandler.c | |
| parent | 35a7249183d2e791eb00b41332e6277c504cdd49 (diff) | |
| download | coreboot-9b143e1474f425b6d81bf6490d67baf26d03c437.tar.xz | |
intel/i82801ix: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3809
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/i82801ix/smihandler.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/smihandler.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 5b6eafaec2..6d176217d1 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -344,7 +344,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -358,7 +358,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_mmio_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -501,7 +501,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u32 smi_sts; /* Update global variable pmbase */ - pmbase = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc; /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. |