device: Use pcidev_on_root()

Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

5 files changed, 12 insertions, 12 deletions

diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 797856ea78..46838fcbf4 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -58,7 +58,7 @@ static void i82801ix_pcie_init(const config_t *const info)
 
 	/* PCIe - BIOS must program... */
 	for (i = 0; i < 6; ++i) {
-		pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i));
+		pciePort[i] = pcidev_on_root(0x1c, i);
 		if (!pciePort[i]) {
 			printk(BIOS_EMERG, "PCIe port 00:1c.%x", i);
 			die(" is not listed in devicetree.\n");
@@ -68,7 +68,7 @@ static void i82801ix_pcie_init(const config_t *const info)
 		pci_write_config8(pciePort[i], 0x324, 0x40);
 	}
 
-	if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) {
+	if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) {
 		for (i = 0; i < 6; ++i) {
 			if (pciePort[i]->enabled) {
 				reg32 = pci_read_config32(pciePort[i], 0xe8);
@@ -116,10 +116,10 @@ static void i82801ix_pcie_init(const config_t *const info)
 
 static void i82801ix_ehci_init(void)
 {
-	struct device *const pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7));
+	struct device *const pciEHCI1 = pcidev_on_root(0x1d, 7);
 	if (!pciEHCI1)
 		die("EHCI controller (00:1d.7) not listed in devicetree.\n");
-	struct device *const pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7));
+	struct device *const pciEHCI2 = pcidev_on_root(0x1a, 7);
 	if (!pciEHCI2)
 		die("EHCI controller (00:1a.7) not listed in devicetree.\n");
 
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 474c484ad6..b809a4e3b7 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -566,7 +566,7 @@ static const char *lpc_acpi_name(const struct device *dev)
 
 static void southbridge_fill_ssdt(struct device *device)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	struct device *dev = pcidev_on_root(0x1f, 0);
 	config_t *chip = dev->chip_info;
 
 	intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index e35babce28..e3b7e14b8c 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -213,8 +213,7 @@ static void sata_init(struct device *const dev)
 	pci_write_config32(dev, 0x94, sclkcg);
 
 	if (is_mobile && config->sata_traffic_monitor) {
-		struct device *const lpc_dev = dev_find_slot(0,
-							    PCI_DEVFN(0x1f, 0));
+		struct device *const lpc_dev = pcidev_on_root(0x1f, 0);
 		if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF)
 							>> 3) & 3) == 3) {
 			u8 reg8 = pci_read_config8(dev, 0x9c);
diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c
index 9dc9a3b989..74fa495695 100644
--- a/src/southbridge/intel/i82801ix/smi.c
+++ b/src/southbridge/intel/i82801ix/smi.c
@@ -50,7 +50,8 @@ static void smm_relocate(void)
 
 	printk(BIOS_DEBUG, "Initializing SMM handler...");
 
-	pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc;
+	pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), D31F0_PMBASE) &
+									0xfffc;
 	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
 
 	smi_en = inl(pmbase + SMI_EN);
@@ -138,7 +139,7 @@ static void smm_install(void)
 
 	if (!acpi_is_wakeup_s3()) {
 		/* enable the SMM memory window */
-		pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+		pci_write_config8(pcidev_on_root(0, 0), SMRAM,
 					D_OPEN | G_SMRAME | C_BASE_SEG);
 
 		/* copy the real SMM handler */
@@ -148,7 +149,7 @@ static void smm_install(void)
 	}
 
 	/* close the SMM memory window and enable normal SMM */
-	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+	pci_write_config8(pcidev_on_root(0, 0), SMRAM,
 			G_SMRAME | C_BASE_SEG);
 }
 
@@ -176,6 +177,6 @@ void smm_lock(void)
 	 * make the SMM registers writable again.
 	 */
 	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+	pci_write_config8(pcidev_on_root(0, 0), SMRAM,
 			D_LCK | G_SMRAME | C_BASE_SEG);
 }
diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c
index 5f40d2ec7c..931198254d 100644
--- a/src/southbridge/intel/i82801ix/thermal.c
+++ b/src/southbridge/intel/i82801ix/thermal.c
@@ -24,7 +24,7 @@
 
 static void thermal_init(struct device *dev)
 {
-	if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0))))
+	if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0)))
 		return;
 
 	u8 reg8;