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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-21 18:35:37 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-01 01:54:08 +0000
commitdf128a55b183d3d7a6d7ae986f33abffac50f371 (patch)
tree66f2cef1c9f2516da2783cb945b99f8223e74046 /src/southbridge/intel/i82801ix
parenta84a7340b6291e209db2d5a3a28507816eec2223 (diff)
downloadcoreboot-df128a55b183d3d7a6d7ae986f33abffac50f371.tar.xz
intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL
This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
-rw-r--r--src/southbridge/intel/i82801ix/pcie.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index 3b90ce6471..b1d0ecc214 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@@ -41,10 +42,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);