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authorAngel Pons <th3fanbus@gmail.com>2020-10-30 17:36:16 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-07 14:18:20 +0000
commit4b519f7c62d55b06c1d99ee6b39a0226475777ad (patch)
treef413f852122f395bc70793572956a80b5e8cbf9b /src/southbridge/intel/i82801ix
parent344a1bd43c63dbfeb3cff04e63d531f32242aba4 (diff)
downloadcoreboot-4b519f7c62d55b06c1d99ee6b39a0226475777ad.tar.xz
sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits
For all these southbridges, the lower nibble of PCICMD is read-only. Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change. Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index ad7141ac49..652da54103 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -355,11 +355,6 @@ static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
- /* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-
/* IO APIC initialization. */
i82801ix_enable_apic(dev);