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authorPatrick Rudolph <siro@das-labor.org>2018-11-26 15:56:11 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-12-05 16:57:04 +0000
commit4af2add608eb0848f2c3105f0b29457b5b3ce138 (patch)
tree49f338c6d848c9be7a7a6170f0452ac54ea569b2 /src/southbridge/intel/i82801ix
parent571477b514f591d6db3a71142a135b25d07f2c3e (diff)
downloadcoreboot-4af2add608eb0848f2c3105f0b29457b5b3ce138.tar.xz
sb/intel: Fix pointer casts
Fix some compiler warnings due to pointer to integer conversions with different size. Required for 64bit ramstage. Change-Id: Ibfb3cacf25adfb4a242d38e4ea290fdc3929a684 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
-rw-r--r--src/southbridge/intel/i82801ix/hdaudio.c2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ix/sata.c7
3 files changed, 8 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index 607604b78b..b4cee4633c 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -278,7 +278,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index a69b8796ac..474c484ad6 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -553,7 +553,7 @@ static void southbridge_inject_dsdt(struct device *dev)
/* Add it to SSDT. */
acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
acpigen_pop_len();
}
}
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index dcdeeb40d7..e35babce28 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -30,9 +30,14 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
{
int i;
u32 reg32;
+ struct resource *res;
/* Initialize AHCI memory-mapped space */
- u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ res = find_resource(dev, PCI_BASE_ADDRESS_5);
+ if (!res)
+ return;
+
+ u8 *abar = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Set AHCI access mode.