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authorPeter Lemenkov <lemenkov@gmail.com>2018-10-23 11:12:46 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-01-14 11:56:38 +0000
commit7b42811fa55bb5ea67c8dc71cd9436cd8ddd83c3 (patch)
tree94dd4dcd1d56127b41b37603c3ef491850b969f5 /src/southbridge/intel/i82801ix
parentaa6d38859768486d3353edd7aef092b6318ac1bf (diff)
downloadcoreboot-7b42811fa55bb5ea67c8dc71cd9436cd8ddd83c3.tar.xz
sb/intel: Use common RCBA MACROs
This commit follows up on commit 2e464cf3 with Change-Id I61fb3b01ff15ba2da2ee938addfa630c282c9870. Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
-rw-r--r--src/southbridge/intel/i82801ix/early_init.c2
-rw-r--r--src/southbridge/intel/i82801ix/i82801ix.h1
2 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index c40f9b73ea..f7e2fd2621 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -22,7 +22,7 @@ void i82801ix_early_init(void)
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
/* Set up RCBA. */
- pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+ pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Set up PMBASE. */
pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index f094ed8920..ddecc0cd71 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -111,7 +111,6 @@
#define D31F0_CxSTATE_CNF 0xa9
#define D31F0_C4TIMING_CNT 0xaa
#define D31F0_GPIO_ROUT 0xb8
-#define D31F0_RCBA 0xf0
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)