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authorPatrick Rudolph <siro@das-labor.org>2017-06-11 17:05:17 +0200
committerPatrick Rudolph <siro@das-labor.org>2017-08-27 13:07:09 +0000
commit959dfc1261074e50404cb1d435729c62a054ddb9 (patch)
tree9d3664b8c1fd5c2dec6798a0078c47fedcfa7480 /src/southbridge/intel/i82801ix
parent3f3025d7f1adc0fa1a405f14a0cbb6e4e319afe0 (diff)
downloadcoreboot-959dfc1261074e50404cb1d435729c62a054ddb9.tar.xz
sb/intel/*/nvs: Rename register
Rename register to match recent intel models. Required for Lenovo H8 to operate on all generations. Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
-rw-r--r--src/southbridge/intel/i82801ix/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/i82801ix/nvs.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index df8306441a..97d9fa9f82 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -51,11 +51,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Thermal policy */
Offset (0x14),
ACTT, 8, // 0x14 - active trip point
- PSVT, 8, // 0x15 - passive trip point
+ TPSV, 8, // 0x15 - passive trip point
TC1V, 8, // 0x16 - passive trip point TC1
TC2V, 8, // 0x17 - passive trip point TC2
TSPV, 8, // 0x18 - passive trip point TSP
- CRTT, 8, // 0x19 - critical trip point
+ TCRT, 8, // 0x19 - critical trip point
DTSE, 8, // 0x1a - Digital Thermal Sensor enable
DTS1, 8, // 0x1b - DT sensor 1
DTS2, 8, // 0x1c - DT sensor 2
diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h
index c3a3920596..decea53438 100644
--- a/src/southbridge/intel/i82801ix/nvs.h
+++ b/src/southbridge/intel/i82801ix/nvs.h
@@ -35,11 +35,11 @@ typedef struct {
u8 dckn; /* 0x13 - PCIe docking state */
/* Thermal policy */
u8 actt; /* 0x14 - active trip point */
- u8 psvt; /* 0x15 - passive trip point */
+ u8 tpsv; /* 0x15 - passive trip point */
u8 tc1v; /* 0x16 - passive trip point TC1 */
u8 tc2v; /* 0x17 - passive trip point TC2 */
u8 tspv; /* 0x18 - passive trip point TSP */
- u8 crtt; /* 0x19 - critical trip point */
+ u8 tcrt; /* 0x19 - critical trip point */
u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
u8 dts1; /* 0x1b - DT sensor 1 */
u8 dts2; /* 0x1c - DT sensor 2 */