diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/intel/i82801ix | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
| -rw-r--r-- | src/southbridge/intel/i82801ix/acpi/sleepstates.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/lpc.c | 6 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl index d7fb2a56bb..79818a109a 100644 --- a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl +++ b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl @@ -15,7 +15,7 @@ */ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !CONFIG(HAVE_ACPI_RESUME) Name(\_S1, Package(){0x1,0x0,0x0,0x0}) #else Name(\_S3, Package(){0x5,0x0,0x0,0x0}) diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 991ae82259..99078dc402 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -224,7 +224,7 @@ static void i82801ix_init(void *chip_info) i82801ix_hide_functions(); /* Reset watchdog timer. */ -#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if !CONFIG(HAVE_SMI_HANDLER) outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ #endif outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index bfa875b74d..421a101bdc 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -28,7 +28,7 @@ #include <southbridge/intel/common/rcba.h> -#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) +#if CONFIG(BOARD_EMULATION_QEMU_X86_Q35) /* * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a * non-conflicting address. No need to worry about speedstep, it diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index db5d3a641a..79a1a1d03f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -370,7 +370,7 @@ static void enable_clock_gating(void) RCBA32(0x38c0) |= 7; } -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) static void i82801ix_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN @@ -394,7 +394,7 @@ static void i82801ix_lock_smm(struct device *dev) /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + if (!CONFIG(PARALLEL_MP)) smm_lock(); #if TEST_SMM_FLASH_LOCKDOWN @@ -466,7 +466,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) i82801ix_lock_smm(dev); #endif } |