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authorArthur Heymans <arthur@aheymans.xyz>2017-12-24 08:11:13 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-06-29 07:45:30 +0000
commita8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23 (patch)
treeb674190e4efe1c2a814a2638b3a20d92701c353d /src/southbridge/intel/i82801jx/Kconfig
parente798e6a0b946fe5a3964bc38fb7783a219adf177 (diff)
downloadcoreboot-a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23.tar.xz
sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables
Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/Kconfig')
-rw-r--r--src/southbridge/intel/i82801jx/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index e418a94f60..2c98f72e4b 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
+ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select IOAPIC
select HAVE_USBDEBUG
select HAVE_HARD_RESET