summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801jx/Makefile.inc
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-11-09 14:29:04 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-12 18:23:07 +0000
commitc484da1a98610d783131a3a3998c0a999b97f9f5 (patch)
treec4e25f9b4fbde15a9962b9d0c7d7117997e26ad1 /src/southbridge/intel/i82801jx/Makefile.inc
parentfecf77770b8e68b9ef82021ca53c31db93736d93 (diff)
downloadcoreboot-c484da1a98610d783131a3a3998c0a999b97f9f5.tar.xz
sb/intel/i82801jx: Add common code for LPC decode
Change-Id: Id706da33f06ceeec39ea50301130770226f0474e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/Makefile.inc')
-rw-r--r--src/southbridge/intel/i82801jx/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc
index 02da8146e9..30ed351970 100644
--- a/src/southbridge/intel/i82801jx/Makefile.inc
+++ b/src/southbridge/intel/i82801jx/Makefile.inc
@@ -31,6 +31,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
smm-y += smihandler.c
+romstage-y += early_init.c
romstage-y += early_smbus.c
endif