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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 19:58:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-13 09:22:50 +0000 |
| commit | 87074f904219744291f4fd56e0241d40f2dd583a (patch) | |
| tree | e86907e79fbab691ee33b710724a25af33a85259 /src/southbridge/intel/i82801jx/bootblock.c | |
| parent | dc972e17c70a7ca0ffe5e5ed1613838d48fe72a0 (diff) | |
| download | coreboot-87074f904219744291f4fd56e0241d40f2dd583a.tar.xz | |
sb/intel/i82801jx: Enable upper 128bytes of CMOS
The normal romcc bootblock uses this.
Change-Id: I60f735f703a9208911f5cc8a81930535e574644d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36755
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/bootblock.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/bootblock.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index fb2d5337b3..01faef34af 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -36,4 +36,7 @@ static void bootblock_southbridge_init(void) /* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Enable upper 128bytes of CMOS. */ + RCBA32(0x3400) = (1 << 2); } |